Self-concatenated code design and its application in power-efficient cooperative communications

In this tutorial, we have focused on the design of binary self-concatenated coding schemes with the help of EXtrinsic Information Transfer (EXIT) charts and Union bound analysis. The design methodology of future iteratively decoded self-concatenated aided cooperative communication schemes is presented. In doing so, we will identify the most important milestones in the area of channel coding, concatenated coding schemes and cooperative communication systems till date and suggest future research directions

Trellis coded modulation techniques

The subject of this thesis is an investigation of various trellis coded modulation (TCM) techniques that have potential for out-performing conventional methods. The primary advantage of TCM over modulation schemes employing traditional error-correction coding is the ability to achieve increased power efficiency without the normal expansion of bandwidth introduced by the coding process. Thus, channels that are power limited and bandwidth limited are an ideal application for TCM. In this thesis, four areas of interest are investigated. These include: signal constellation design, multilevel convolutional coding, adaptive TCM and finally low-complexity implementation of TCM. An investigation of the effect of signal constellation design on probability of error has led to the optimisation of constellation angles for a given channel signal to noise ratio and a given code. The use of multilevel convolutional codes based on rings of integers and multi-dimensional modulation is presented. The potential benefits of incorporating several modulation schemes with adaptive TCM which require a single decoder are also investigated. The final area of investigation has been the development of an algorithm for decoding of convolutional codes with a low complexity decoder. The research described in this thesis investigated the use of trellis coded modulation to develop various techniques applicable to digital data transmission systems. Throughout this work, emphasis has been placed on enhancing the performance or complexity of conventional communication systems by simple modifications to the existing structures

A hardware implementation of a Viterbi decoder for a (3,2/3) TCM code

The report details the design of a dedicated Viterbi decoder chip set for an Ungerboek (3,2/3) Trellis Coded Modulation code. It was the specific intention of the thesis to design a system that could be implemented on standard Field Programmable Gate Arrays (FPGA) yet still be able to cope with high bit rates. The focus of the research was to both evaluate and modify the existing VLSI design techniques and to develop new techniques to make this possible. Trellis Coded Modulation refers to a specific sub-class of convolutional codes that ire an example of coded modulation. In coded modulation there is a direct link between the encoding and modulation processes aimed at improving the performance of the code by introducing redundancy in the signal set used to transmit the code. Ungerboek developed a technique for mapping the encoded words onto points in the signal set, called mapping by set partitioning, that maximises the Euclidian distance between adjacent codewords, and hence maximises the minimum distance between any two output sequences in the code. The Viterbi algorithm is a maximum likelihood decoder for convolutional codes such as TCM. The operation of the Viterbi algorithm is based on using soft decision decoding to produce an estimate of how well the received sequence corresponds with any of the allowed code sequences. The code sequences which most closely matches the received sequence is then decoded to form the output of the decoder. A central problem in implementing systems using TCM with Viterbi decoding is that although the encoder is a relatively simple device, the decoder is not. The complexity of the Viterbi decoder for any given TCM scheme will be the major drawback in implementing the scheme. As such techniques for reducing the complexity of Viterbi decoders are of interest to developers of communication systems. The algorithms describing the implementation and operation of the Viterbi algorithm can be categorised into three main layers. The top layer holds the theoretical algorithm itself, in the second layer are the set of algorithms that describe the broad techniques used to manipulate the theoretical algorithm into a form in which it can be implemented, and the third layer of algorithms describe the implementations themselves. The work contained in this thesis concentrates on the second two layers of algorithms

Spinal codes

Spinal codes are a new class of rateless codes that enable wireless networks to cope with time-varying channel conditions in a natural way, without requiring any explicit bit rate selection. The key idea in the code is the sequential application of a pseudo-random hash function to the message bits to produce a sequence of coded symbols for transmission. This encoding ensures that two input messages that differ in even one bit lead to very different coded sequences after the point at which they differ, providing good resilience to noise and bit errors. To decode spinal codes, this paper develops an approximate maximum-likelihood decoder, called the bubble decoder, which runs in time polynomial in the message size and achieves the Shannon capacity over both additive white Gaussian noise (AWGN) and binary symmetric channel (BSC) models. Experimental results obtained from a software implementation of a linear-time decoder show that spinal codes achieve higher throughput than fixed-rate LDPC codes, rateless Raptor codes, and the layered rateless coding approach of Strider, across a range of channel conditions and message sizes. An early hardware prototype that can decode at 10 Mbits/s in FPGA demonstrates that spinal codes are a practical construction.Massachusetts Institute of Technology (Irwin and Joan Jacobs Presidential Fellowship)Massachusetts Institute of Technology (Claude E. Shannon Assistantship)Intel Corporation (Intel Fellowship

The development of an error-correcting scheme for use with a six-tone HF modem

This thesis describes the development of an error correcting system for a H.F. modem employing 6-tone Multi-Frequency Shift Keying (MFSK) as its modulation scheme. The modulation scheme was chosen to be compatible with equipment already in service and to eliminate the need to modify the existing communications infrastructure. A convolutional code together with either Viterbi decoding or Fano decoding is chosen to provide the error correction because of the potential power of such codes and because it is possible for these combinations of code and decoding method to work with any alphabet size. To detect whether correction has been successful a Cyclic Redundancy Check (CRC) is embedded within the data block before encoding.A method of using a convolutional code to provide variable rate is presented. The method uses a systematic code so that it is possible for the scheme to have a quick look to see if the first data transmission has been received error free. A search for good codes is undertaken and the effect the alphabet size has on the code spectra discussed. It is shown that a good generator sequence for a binary code is also a good generator sequence for non-binary codes.To decode the convolutional code both the Viterbi maximum likelihood decoder and the Fano sequential decoder are studied. It is argued that the Fano sequential decoder is the better choice for this application because it makes better use of system resources which will be limited in the field equipment. It is also shown that the performance of multi-level codes is better than binary codes and that an alphabet size of around 6 is optimum.The throughput of the variable rate scheme and a number of fixed rate schemes is examined. It is shown that the variable rate scheme provides the best throughput at all data rates and that the throughput improvement at the higher data rates is greatest. The effect of interleaving is also examined and results presented.To support the variable rate scheme a protocol is developed that can be used on practical H.F. channels. The potential problems with errors on both the forward and return channel are analysed and mechanisms to deal with these built-in