58,360 research outputs found
Challenging the evolutionary strategy for synthesis of analogue computational circuits
There are very few reports in the past on applications of Evolutionary Strategy (ES) towards the synthesis of analogue circuits. Moreover, even fewer reports are on the synthesis of computational circuits. Last fact is mainly due to the dif-ficulty in designing of the complex nonlinear functions that these circuits perform. In this paper, the evolving power of the ES is challenged to design four computational circuits: cube root, cubing, square root and squaring functions. The synthesis succeeded due to the usage of oscillating length genotype strategy and the substructure reuse. The approach is characterized by its simplicity and represents one of the first attempts of application of ES towards the synthesis of âQRâ circuits. The obtained experimental results significantly exceed the results published before in terms of the circuit quality, economy in components and computing resources utilized, revealing the great potential of the technique pro-posed to design large scale analog circuits
Absolutely free extrinsic evolution of passive low-pass filter
Evolutionary electronics is a brunch of evolvable hardware, where the evolutionary algorithm is applied towards electronic circuits. The success of evolutionary search most of all depends on variable length representation methodology. The low-pass filter is a standard task in evolutionary electronics to start with. The results of evolution enable one to qualify whether the methodology is good for further experiments. In this paper the maximum freedom for evolutionary search has been proclaimed as a main target during development of new VLR methodology. The introduction of R-support elements enables to perform an unconstrained evolution of analogue circuits for the first time. The proposed algorithm has been tested on the example of analogue low-pass filter. The experimental results demonstrate that the evolved filter is comparable with filters evolved previously using genetic programming and genetic algorithms techniques. The obtained results are compared in details with low-pass filters previously designed
Open-ended evolution to discover analogue circuits for beyond conventional applications
This is the author's accepted manuscript. The final publication is available at Springer via http://dx.doi.org/10.1007/s10710-012-9163-8. Copyright @ Springer 2012.Analogue circuits synthesised by means of open-ended evolutionary algorithms often have unconventional designs. However, these circuits are typically highly compact, and the general nature of the evolutionary search methodology allows such designs to be used in many applications. Previous work on the evolutionary design of analogue circuits has focused on circuits that lie well within analogue application domain. In contrast, our paper considers the evolution of analogue circuits that are usually synthesised in digital logic. We have developed four computational circuits, two voltage distributor circuits and a time interval metre circuit. The approach, despite its simplicity, succeeds over the design tasks owing to the employment of substructure reuse and incremental evolution. Our findings expand the range of applications that are considered suitable for evolutionary electronics
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Automatic synthesis of analog layout : a survey
A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon
Automated Circuit Approximation Method Driven by Data Distribution
We propose an application-tailored data-driven fully automated method for
functional approximation of combinational circuits. We demonstrate how an
application-level error metric such as the classification accuracy can be
translated to a component-level error metric needed for an efficient and fast
search in the space of approximate low-level components that are used in the
application. This is possible by employing a weighted mean error distance
(WMED) metric for steering the circuit approximation process which is conducted
by means of genetic programming. WMED introduces a set of weights (calculated
from the data distribution measured on a selected signal in a given
application) determining the importance of each input vector for the
approximation process. The method is evaluated using synthetic benchmarks and
application-specific approximate MAC (multiply-and-accumulate) units that are
designed to provide the best trade-offs between the classification accuracy and
power consumption of two image classifiers based on neural networks.Comment: Accepted for publication at Design, Automation and Test in Europe
(DATE 2019). Florence, Ital
Evolutionary Synthesis of Analog Electronic Circuits Using EDA Algorithms
DisertaÄnĂ prĂĄce je zamÄĹena na nĂĄvrh analogovĂ˝ch elektronickĂ˝ch obvodĹŻ pomocĂ algoritmĹŻ s pravÄpodobnostnĂmi modely (algoritmy EDA). PrezentovanĂŠ metody jsou na zĂĄkladÄ poĹžadovanĂ˝ch charakteristik cĂlovĂ˝ch obvodĹŻ schopny navrhnout jak parametry pouĹžitĂ˝ch komponent tak takĂŠ jejich topologii zapojenĂ. TĹi rĹŻznĂŠ metody vyuĹžitĂ EDA algoritmĹŻ jsou navrĹženy a otestovĂĄny na pĹĂkladech skuteÄnĂ˝ch problĂŠmĹŻ z oblasti analogovĂ˝ch elektronickĂ˝ch obvodĹŻ. PrvnĂ metoda je urÄena pro nĂĄvrh pasivnĂch analogovĂ˝ch obvodĹŻ a vyuĹžĂvĂĄ algoritmus UMDA pro nĂĄvrh jak topologie zapojenĂ tak takĂŠ hodnot parametrĹŻ pouĹžitĂ˝ch komponent. Metoda je pouĹžita pro nĂĄvrh admitanÄnĂ sĂtÄ s poĹžadovanou vstupnĂ impedancĂ pro ĂşÄely chaotickĂŠho oscilĂĄtoru. DruhĂĄ metoda je takĂŠ urÄena pro nĂĄvrh pasivnĂch analogovĂ˝ch obvodĹŻ a vyuĹžĂvĂĄ hybridnĂ pĹĂstup - UMDA pro nĂĄvrh topologie a metodu lokĂĄlnĂ optimalizace pro nĂĄvrh parametrĹŻ komponent. TĹetĂ metoda umoĹžĹuje nĂĄvrh analogovĂ˝ch obvodĹŻ obsahujĂcĂch takĂŠ tranzistory. Metoda vyuĹžĂvĂĄ hybridnĂ pĹĂstup - EDA algoritmus pro syntĂŠzu topologie a metoda lokĂĄlnĂ optimalizace pro urÄenĂ parametrĹŻ pouĹžitĂ˝ch komponent. Informace o topologii je v jednotlivĂ˝ch jedincĂch populace vyjĂĄdĹena pomocĂ grafĹŻ a hypergrafĹŻ.Dissertation thesis is focused on design of analog electronic circuits using Estimation of Distribution Algorithms (EDA). Based on the desired characteristics of the target circuits the proposed methods are able to design the parameters of the used components and theirs topology of connection as well. Three different methods employing EDA algorithms are proposed and verified on examples of real problems from the area of analog circuits design. The first method is capable to design passive analog circuits. The method employs UMDA algorithm which is used for determination of the parameters of the used components and synthesis of the topology of their connection as well. The method is verified on the problem of design of admittance network with desired input impedance function which is used as a part of chaotic oscillator circuit. The second method is also capable to design passive analog circuits. The method employs hybrid approach - UMDA for synthesis of the topology and local optimization method for determination of the parameters of the components. The third method is capable to design analog circuits which include also ac- tive components such as transistors. Hybrid approach is used. The topology is synthesized using EDA algorithm and the parameters are determined using a local optimization method. In the individuals of the population information about the topology is represented using graphs and hypergraphs.
Unconstrained evolution of close-to-ideal "LCR" low-pass filter
The unconstrained evolution has already been applied in the past towards design of digital circuits, and extraordinary results have been obtained, including generation of more compact circuits with smaller number of electronic components. In this paper the unconstrained evolution method is developed for analogue circuits. At first, the method is probed on the design of analogue low-pass filter with standard transition band. The algorithm produced the best results in terms of quality of the circuits evolved and evolutionary resources required. Then, the new methodology is applied towards more sophisticated task, the close-to-ideal low-pass filter. The new methodology developed differs from previous ones by its simplicity and represents one of the first attempts to apply evolutionary strategy towards the analogue circuit design. The obtained results are compared in details with low-pass filters previously designed
Constrained and unconstrained evolution of â LCRâ low-pass filters with oscillating length representation
The unconstrained evolution has already been applied in the past towards design of digital circuits, and extraordinary results have been obtained, including generation of circuits with smaller number of electronic components. In this paper both constrained and unconstrained evolutions, blended with oscillating length genotype sweeping strategy, are applied towards design of analogue â LCRâ circuits. The comparison of both evolutions is made and the promising results are obtained. The new algorithm has produced the best results in terms of quality of the circuits evolved and evolutionary resources required. It differs from previous ones by its simplicity and represents one of the first attempts to apply Evolutionary Strategy towards the analogue circuit design. The obtained results are compared in details with low-pass filters previously designed
Geometrically-constrained, parasitic-aware synthesis of analog ICs
In order to speed up the design process of analog ICs, iterations between different design stages should be avoided as much as possible. More specifically, spins between electrical and physical synthesis should be reduced for this is a very time-consuming task: if circuit performance including layout-induced degradations proves unacceptable, a re-design cycle must be entered, and electrical, physical, or both synthesis processes, would have to be repeated. It is also worth noting that if geometric optimization (e.g., area minimization) is undertaken after electrical synthesis, it may add up as another source of unexpected degradation of the circuit performance due to the impact of the geometric variables (e.g., transistor folds) on the device and the routing parasitic values. This awkward scenario is caused by the complete separation of said electrical and physical synthesis, a design practice commonly followed so far. Parasitic-aware synthesis, consisting in including parasitic estimates to the circuit netlist directly during electrical synthesis, has been proposed as solution. While most of the reported contributions either tackle parasitic-aware synthesis without paying special attention to geometric optimization or approach both issues only partially, this paper addresses the problem in a unified way. In what has been called layout-aware electrical synthesis, a simulation-based optimization algorithm explores the design space with geometric variables constrained to meet certain user-defined goals, which provides reliable estimates of layout-induced parasitics at each iteration, and, thereby, accurate evaluation of the circuit ultimate performance. This technique, demonstrated here through several design examples, requires knowing layout details beforehand; to facilitate this, procedural layout generation is used as physical synthesis approach due to its rapidness and ability to capture analog layout know-how.Ministerio de EducaciĂłn y Ciencia TEC2004-0175
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