SEED modeling of an ESD gun discharge to a USB cable

“An IC protected by a transient voltage suppression (TVS) diode may fail if the TVS device does not turn on or does not turn on quickly enough, causing the IC to take the full brunt of the electrostatic discharge (ESD) event. Transient simulation models have been developed for ESD protection devices for the purpose of system-efficient ESD design (SEED). The TVS modeling methodology has been improved to better represent the physics that occurs during the TVS response and more accurately predict the interactions between off-chip and on-chip protection devices. Moreover, a complicated test scenario -- an ESD gun discharge through a USB cable -- was investigated and simulated, to demonstrate the impact of position, grounding condition, and quality of the USB cable. Test and design guidelines are proposed for incorporating a USB cable in a contact-discharge ESD test. At the beginning, a hybrid simulation approach was proposed, which uses a full-wave model of the ESD gun, cable, and enclosure combined with the ESD protection devices and test board’s circuit-level models. The voltage and current of ESD protection devices are captured within 24-35% compared to the measurements, under various cable configurations. To further improve the simulation accuracy, physics-based modeling methodologies were proposed to improve the previously developed TVS model, especially on the falling edge after the overshoot. The ESD protection device’s response was studied in simulation and measurement for various cable configurations. And the overall discrepancy is within 30%. The modeling process can help engineers to evaluate the design effectiveness under various complicated test scenarios”--Abstract, page iv

Characterization and modeling of ESD events, risk and protection

“The ESD (Electrostatic discharge) failures have been raising critical reliability problems in electronic devices design. However, not all the ESD scenarios have been specified by the IEC standard and the characterizations of the ESD risk for different scenarios are essential to evaluate the ESD robustness of the devices in the real word. The insulation of plastic enclosures provides protection against ESD to the electronic system inside. However, seams between plastic parts are often unavoidable. Different plastic arrangements are constructed to investigate the spark length and current derivatives and to understand the ESD spark behavior for geometries having spark lengths longer than the values predicted by Paschen’s law. For the wearable devices, the core difference between the posture assumed for IEC 61000-4-2 human metal discharge and a discharge to a wearable device is the impedance between the charged body and the grounded structure discharged to. The results show that the current measured in the brush-by scenario can reach values twice as high as the current specified in the IEC standard. A simulation model using the measured impedance and Rompe and Weizel’s law provides predictions on the peak current derivative when the spark length is varied. The increasing peak current derivative with shorter spark length indicates stronger field coupling to the devices. SEED(System-efficient ESD design) modeling helps the designer to predict the ESD risk at the early stage, an accurate TVS model can be used to study the transient response of the external TVS and the on-chip protection when applied in a typical high-speed input/output (I/O) interface”--Abstract, page iv

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process

Novel Rail Clamp Architectures and Their Systematic Design

abstract: Rail clamp circuits are widely used for electrostatic discharge (ESD) protection in semiconductor products today. A step-by-step design procedure for the traditional RC and single-inverter-based rail clamp circuit and the design, simulation, implementation, and operation of two novel rail clamp circuits are described for use in the ESD protection of complementary metal-oxide-semiconductor (CMOS) circuits. The step-by-step design procedure for the traditional circuit is technology-node independent, can be fully automated, and aims to achieve a minimal area design that meets specified leakage and ESD specifications under all valid process, voltage, and temperature (PVT) conditions. The first novel rail clamp circuit presented employs a comparator inside the traditional circuit to reduce the value of the time constant needed. The second circuit uses a dynamic time constant approach in which the value of the time constant is dynamically adjusted after the clamp is triggered. Important metrics for the two new circuits such as ESD performance, latch-on immunity, clamp recovery time, supply noise immunity, fastest power-on time supported, and area are evaluated over an industry-standard PVT space using SPICE simulations and measurements on a fabricated 40 nm test chip.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Area Efficient Device Optimization for ESD Protection in High Speed Interface ICs

Electrostatic discharge (ESD) protection is considered as a vital step in integrated circuit (IC) manufacturing process. IC chips are unable to overcome the effects of transient events without adequate discharge protection. Recent trend in the industry has seen the incorporation of system level ESD protection within the IC chip. Incorporating system level on-chip ESD protection often increases cost, degrades circuit performance and consumes layout area which could otherwise be used for improving the circuit performance. These design challenges could be easily overcome if the parasitic components in a circuit were used for ESD protection. Despite the various design challenges, on-chip ESD protection is still desirable as it saves the area on the circuit board by eliminating the traditional ESD protection devices resulting in more compact circuits. Furthermore, using parasitic components while designing on-chip system level ESD protection can save layout area. In order to effectively implement this solution, a study on ESD events, protection circuits and high-speed ICs was carried out. Different types of ESD events and the different models pertaining to ESD events were studied and are discussed in detail. An overview of high-speed integrated circuits was also carried out with emphasis on the protection topologies that are commonly used. The ESD characteristics of parasitic PNP devices in rail-based ESD protection structure was then studied to summarize its viability as a protection circuit. The turn-on or breakdown voltage of the parasitic PNP is studied by technology computer aided design (TCAD) simulations performed in Silvaco software. The breakdown voltage, holding voltage, on resistance and failure current were studied and modeled to maximize ESD protection

Optimization and modeling of ESD protection devices

“Transient voltage suppressors (TVS) are used to protect ICs (integrated circuits) against overvoltage, ESD (Electrostatic Discharge), inductive load switching, and even lightning strikes. In this research, a transient behavior model framework for ESD protection devices is used for modelling four different types of TVS (non-snapback, snapback, spark gap like device and varistor). The System-Efficient ESD Design (SEED) methodology is utilized to strengthen the trust in the model framework by efficient simulation of ESD interaction of the off-chip ESD protection devices with the IC ESD protection device and associated measurement data. Improvements in the TVS transient response, accounting for conductivity modulation, voltage overshot at the snapback voltage, etc., are required to accurately model the ESD protection device. With this in mind, the unimproved model is presented for various ESD protection device where their transient behavior of single component can be fully described by a quasistatic very fast transmission line pulse (VF)-TLP. The improved model is validated within a sub-system consisting of an off-chip ESD protection device, an IC on-chip protection and a PCB trace in between. Multiple solutions to avoid convergence issues are also proposed for effective simulation”--Abstract, page iv

A Physics-Based Model For Snapback-Type ESD Protection Devices

A simplified physical-based model for deep-snapback transient voltage suppressors (TVS) is developed in this article. While based on physics, the number of parameters and components is minimized, so the model can be tuned easily from available measurements of the packaged TVS. SPICE convergence issues seen in previous snapback device models are eliminated by adding nonlinear damping components to the model. No convergence issues were seen among any of the simulations performed for this study, which includes transmission-line pulse tests with multiple levels and rise times. The proposed model was used to represent two different TVS devices and was validated in both device- and system-level simulations. Simulations of quasi-static and transient behavior matched measurement results within about 20% among all the tested cases

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

System efficient ESD design concept for soft failures

This research covers the topic of developing a systematic methodology of studying electrostatic discharge (ESD)-induced soft failures. ESD-induced soft failures (SF) are non-destructive disruptions of the functionality of an electronic system. The soft failure robustness of a USB3 Gen 1 interface is investigated, modeled, and improved. The injection is performed directly using transmission line pulser (TLP) with varying: pulse width, amplitude, polarity. Characterization provides data for failure thresholds and a SPICE circuit model that describes the transient voltage and current at the victim. Using the injected current, the likelihood of a SF is predicted. ESD protection by transient voltage suppressor (TVS) diodes is numerically simulated in several configurations. The results strongly suggest the viability of using well-established hard failure mitigation techniques for improving SF robustness, and the possibility of using numerical simulation for optimization purposes. A concept of soft failure system efficient ESD design (SF-SEED) is proposed and shown to be effective --Abstract, page iv