A chaotic switched-capacitor circuit for characteristic CMOS noise distributions generation

A switched-capacitor circuit is proposed for the generation of noise resembling the typical noise spectral density of MOS devices. The circuit is based on the combination of two chaotic maps, one generating 1/f noise (hopping map) and the other generating white noise (Bernoulli map). Through a programmable weighted adder stage, the contribution of each map can be controlled and, thereby, the position of the corner frequency. Behavioral models simulations were carried out to prove the correct functionality of the proposed approach.Ministerio de Economía y Competitividad TEC2016-80923-

Integrated Circuitry to Detect Slippage Inspired by Human Skin and Artificial Retinas

This paper presents a bioinspired integrated tactile coprocessor that is able to generate a warning in the case of slippage via the data provided by a tactile sensor. Some implementations use different layers of piezoresistive and piezoelectric materials to build upon the raw sensor and obtain the static (pressure) as well as the dynamic (slippage) information. In this paper, a simple raw sensor is used, and a circuitry is implemented, which is able to extract the dynamic information from a single piezoresistive layer. The circuitry was inspired by structures found in human skin and retina, as they are biological systems made up of a dense network of receptors. It is largely based on an artificial retina , which is able to detect motion by using relatively simple spatial temporal dynamics. The circuitry was adapted to respond in the bandwidth of microvibrations produced by early slippage, resembling human skin. Experimental measurements from a chip implemented in a 0.35-mum four-metal two-poly standard CMOS process are presented to show both the performance of the building blocks included in each processing node and the operation of the whole system as a detector of early slippage.Ministerio de Economía y Competitividad TEC2006-12376-C02-01Gobierno de España TEC2006- 1572

Circuit paradigm in the 21

reviewe

34th Midwest Symposium on Circuits and Systems-Final Program

Organized by the Naval Postgraduate School Monterey California. Cosponsored by the IEEE Circuits and Systems Society. Symposium Organizing Committee: General Chairman-Sherif Michael, Technical Program-Roberto Cristi, Publications-Michael Soderstrand, Special Sessions- Charles W. Therrien, Publicity: Jeffrey Burl, Finance: Ralph Hippenstiel, and Local Arrangements: Barbara Cristi

A novel true random number generator based on a stochastic diffusive memristor

The intrinsic variability of switching behavior in memristors has been a major obstacle to their adoption as the next generation universal memory. On the other hand, this natural stochasticity can be valuable for hardware security applications. Here we propose and demonstrate a novel true random number generator (TRNG) utilizing the stochastic delay time of threshold switching in a Ag:SiO2 diffusive memristor, which exhibits evident advantages in scalability, circuit complexity and power consumption. The random bits generated by the diffusive memristor TRNG passed all 15 NIST randomness tests without any post-processing, a first for memristive-switching TRNGs. Based on nanoparticle dynamic simulation and analytical estimates, we attributed the stochasticity in delay time to the probabilistic process by which Ag particles detach from a Ag reservoir. This work paves the way for memristors in hardware security applications for the era of Internet of Things (IoT)

Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices

Stochastic Memory Devices for Security and Computing

With the widespread use of mobile computing and internet of things, secured communication and chip authentication have become extremely important. Hardware-based security concepts generally provide the best performance in terms of a good standard of security, low power consumption, and large-area density. In these concepts, the stochastic properties of nanoscale devices, such as the physical and geometrical variations of the process, are harnessed for true random number generators (TRNGs) and physical unclonable functions (PUFs). Emerging memory devices, such as resistive-switching memory (RRAM), phase-change memory (PCM), and spin-transfer torque magnetic memory (STT-MRAM), rely on a unique combination of physical mechanisms for transport and switching, thus appear to be an ideal source of entropy for TRNGs and PUFs. An overview of stochastic phenomena in memory devices and their use for developing security and computing primitives is provided. First, a broad classification of methods to generate true random numbers via the stochastic properties of nanoscale devices is presented. Then, practical implementations of stochastic TRNGs, such as hardware security and stochastic computing, are shown. Finally, future challenges to stochastic memory development are discussed

PUFs based on Coupled Oscillators Static Entropy

We live in a digital era, this led to a shift from traditional industry to a society focused on information and communication technologies. The amount of shared information is exponen- tially growing every year. Protecting all this shared information is keeping everyone’s privacy, is making sure the information is authentic, is keeping everyone safe. The solution for such problems is cryptography using hardware-based, System on Chip, SoC solutions such as Random Number Generators, RNGs, and Physical Unclonable Functions, PUFs. RNGs generate random keys from random processes that occurs inside the system. PUFs generate fixed random keys using random processes that originated in the fabrication process of the chip. The objective of this work is to study and compare a static entropy source based on coupled relaxation oscillators against a state-of-the-art architecture like the static entropy source based on ring oscillators, in advanced 130nm technology. The characteristic studied were, area, power consumption, entropy, resistance to temperature, and supply voltage varia- tions. Compared to the ring oscillator implementation, the static entropy source designed showed promising results as a static entropy source, however, it revealed poor results in terms of area, power consumption, and entropy. Such results mean, the coupled relaxation oscillator may not be good at generating random numbers, however, it may be good at keeping its state when under temperature and supply voltage variations.Vivemos numa era digital, o que levou a uma mudança da indústria tradicional para uma sociedade centrada sobre as tecnologias da informação e da comunicação. A quantidade de informação partilhada está a crescer exponencialmente todos os anos. Proteger toda esta in- formação partilhada é manter a privacidade de todos, é garantir que a informação é autêntica, está a manter todos seguros. A solução para tais problemas é a criptografia com base em soluções de hardware, Sys- tem on Chip, SoC tais como Geradores de Números Aleatórios, RNGs e Funções Físicas Inclo- náveis, PUFs. Os RNGs geram chaves aleatórias a partir de processos aleatórios que ocorrem no interior do sistema. Os PUFs geram chaves aleatórias fixas utilizando processos aleatórios que se originaram no processo de fabrico do chip. O principal objetivo deste trabalho é estudar e comparar uma fonte estática de entropia baseada em osciladores de relaxação acoplados contra uma arquitetura de estado de arte como a fonte estática de entropia baseada em osci- ladores de anel, em tecnologia avançada de 130nm. As características estudadas foram, a área, o consumo energia, a entropia, e a resistência à temperatura e variações de tensão de alimen- tação. Em comparação com a implementação do oscilador do anel, a fonte estática de entropia projetada mostrou resultados promissores como fonte estática de entropia, no entanto, reve- lou maus resultados em termos de área, consumo de energia e entropia. Estes resultados sig- nificam que o oscilador de relaxação acoplado pode não ser bom a gerar números aleatórios, no entanto, pode ser bom para manter o seu estado quando sujeito a variações de temperatura e tensão de alimentação