Multi-port Memory Design for Advanced Computer Architectures

In this thesis, we describe and evaluate novel memory designs for multi-port on-chip and off-chip use in advanced computer architectures. We focus on combining multi-porting and evaluating the performance over a range of design parameters. Multi-porting is essential for caches and shared-data systems, especially multi-core System-on-chips (SOC). It can significantly increase the memory access throughput. We evaluate FinFET voltage-mode multi-port SRAM cells using different metrics including leakage current, static noise margin and read/write performance. Simulation results show that single-ended multi-port FinFET SRAMs with isolated read ports offer improved read stability and flexibility over classical double-ended structures at the expense of write performance. By increasing the size of the access transistors, we show that the single-ended multi-port structures can achieve equivalent write performance to the classical double-ended multi-port structure for 9% area overhead. Moreover, compared with CMOS SRAM, FinFET SRAM has better stability and standby power. We also describe new methods for the design of FinFET current-mode multi-port SRAM cells. Current-mode SRAMs avoid the full-swing of the bitline, reducing dynamic power and access time. However, that comes at the cost of voltage drop, which compromises stability. The design proposed in this thesis utilizes the feature of Independent Gate (IG) mode FinFET, which can leverage threshold voltage by controlling the back gate voltage, to merge two transistors into one through high-Vt and low-Vt transistors. This design not only reduces the voltage drop, but it also reduces the area in multi-port current-mode SRAM design. For off-chip memory, we propose a novel two-port 1-read, 1-write (1R1W) phasechange memory (PCM) cell, which significantly reduces the probability of blocking at the bank levels. Different from the traditional PCM cell, the access transistors are at the top and connected to the bitline. We use Verilog-A to model the behavior of Ge2Sb2Te5 (GST: the storage component). We evaluate the performance of the two-port cell by transistor sizing and voltage pumping. Simulation results show that pMOS transistor is more practical than nMOS transistor as the access device when both area and power are considered. The estimated area overhead is 1.7�, compared to single-port PCM cell. In brief, the contribution we make in this thesis is that we propose and evaluate three different kinds of multi-port memories that are favorable for advanced computer architectures

Forced ion migration for chalcogenide phase change memory device

Non-volatile memory devices with two stacked layers of chalcogenide materials comprising the active memory device have been investigated for their potential as phase change memories. The devices tested included GeTe/SnTe, Ge.sub.2Se.sub.3/SnTe, and Ge.sub.2Se.sub.3/SnSe stacks. All devices exhibited resistance switching behavior. The polarity of the applied voltage with respect to the SnTe or SnSe layer was critical to the memory switching properties, due to the electric field induced movement of either Sn or Te into the Ge-chalcogenide layer. One embodiment of the invention is a device comprising a stack of chalcogenide-containing layers which exhibit phase change switching only after a reverse polarity voltage potential is applied across the stack causing ion movement into an adjacent layer and thus "activating" the device to act as a phase change random access memory device or a reconfigurable electronics device when the applied voltage potential is returned to the normal polarity. Another embodiment of the invention is a device that is capable of exhibiting more that two data states

Reconfigurable three-terminal logic devices using phase-change materials

Conventional solid-state and mass storage memories (such as SRAM, DRAM and the hard disk drive HDD) are facing many technological challenges to meet the ever-increasing demand for fast, low power and cheap data storage solutions. This is compounded by the current conventional computer architectures (such as the von Neumann architecture) with separate processing and storage functionalities and hence data transfer bottlenecks and increased silicon footprint. Beyond the von Neumann computer architecture, the combination of arithmetic-logic processing and (collocally) storage circuits provide a new and promising alternative for computer systems that overcome the many limitations of current technology. However, there are many technical challenges that face the implementation of universal blocks of both logic and memory functions using conventional silicon technology (transistor-transistor logic - TTL, and complementary metal oxide semiconductors - CMOS). Phase-change materials, such as Ge2Sb2Te5 (GST), provide a potential complement or replacement to these technologies to provide both processing and, collocally, storage capability. Existing research in phase-change memory technologies focused on two-terminal non-volatile devices for different memory and logic applications due to their ability to achieve logic-resistive switching in nanosecond time scale, their scalability down to few nanometer-scale cells, and low power requirements. To perform logic functionality, current two-terminal phase-change logic devices need to be connected in series or parallel circuits, and require sequential inputs to perform the required logic function (such as NAND and NOR). In this research programme, three-terminal (3T) non-volatile phase-change memories are proposed and investigated as potential alternative logic cells with simultaneous inputs as reconfigurable, non-volatile logic devices. A vertical 3T logic device structure is proposed in this work based on existing phase-change based memory cell architecture and original concept work by Ovshinsky. A comprehensive, multi-physics finite-element model of the vertical 3T device was constructed in Comsol Multiphysics. This model solves Laplace's equation for the electric potential due to the application of voltage sources. The calculated electric potential and fields provide the Joule heating source in the device, which is used to compute the temperature distribution through solution of the heat diffusion equation, which is necessary to activate the thermally-driven phase transition process. The physically realistic and computationally efficient nucleation- growth model was numerically implemented to model the phase change and resistance change in the Ge2Sb2Te5 (GST) phase-change material in the device, which is combined with the finite- element model using the Matlab programming interface. The changes in electrical and thermal conductivities in the GST region are taken into account following the thermally activated phase transformations between the amorphous-crystalline states using effective medium theory. To determine the appropriate voltage and temperature conditions for the SET and RESET operations, and to optimise the materials and thicknesses of the thermal and heating layers in the device, comprehensive steady-state parametric simulations were carried out using the finite-element multi-physics model. Simulations of transient cycles of writing (SET) and erasing (RESET) processes using appropriate voltage pulses were then carried out on the designed vertical 3T device to study the phase transformations for practical reconfigurable logic operations. The simulations indicated excellent resistance contrast between the logic 1 and 0 states, and successfully demonstrated the feasibility of programming the logic functions of NAND and NOR gates using this 3T configuration

A New Approach to the Design, Fabrication, and Testing of Chalcogenide-Based Multi-State Phase-Change Nonvolatile Memory

A new approach to developing, fabricating, and testing chalcogenide-based multi-state phase-change nonvolatile memory (NVM) is presented. A test chip is fabricated through the MOSIS service. Then post processing, in the Boise State University lab, is performed on the chip to add the chalcogenide material that forms the NVM. Each memory bit consists of an NMOS access transistor and the chalcogenide material placed between the metal3 of the test chip, connected to the access device, and a common, to all memory bits, electrode. This paper describes the design of the memory bit and of the test structures used for reliability and radiation testing. Fabrication and postprocessing of the memory are also discussed