1,683 research outputs found

    Implementation of reed solomon error correcting codes

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    In the present world, communication has got many applications such as telephonic conversations etc. in which the messages are encoded into the communication channel and then decoding it at the receiver end. During the transfer of message, the data might get corrupted due to lots of disturbances in the communication channel. So it is necessary for the decoder tool to also have a function of correcting the error that might occur. Reed Solomon codes are type of burst error detecting codes which has got many applications due to its burst error detection and correction nature. My aim of the project is to implement this reed Solomon codes in a VHDL test bench waveform and also to analyse the error probability that is occurring during transmission. To perform this check one can start with simulating reed Solomon codes in MATLAB and then going for simulation in XILINX writing the VHDL code. The encoder and decoder design of reed Solomon codes have got different algorithms. Based on your requirements you can use those algorithms. The difference between the algorithms is that of the computational calculations between them. The complexity of the code depends on the algorithm used. I will be using Linear Feedback Shift Register circuit for designing the encoder

    A decoding procedure for the Reed-Solomon codes

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    A decoding procedure is described for the (n,k) t-error-correcting Reed-Solomon (RS) code, and an implementation of the (31,15) RS code for the I4-TENEX central system. This code can be used for error correction in large archival memory systems. The principal features of the decoder are a Galois field arithmetic unit implemented by microprogramming a microprocessor, and syndrome calculation by using the g(x) encoding shift register. Complete decoding of the (31,15) code is expected to take less than 500 microsecs. The syndrome calculation is performed by hardware using the encoding shift register and a modified Chien search. The error location polynomial is computed by using Lin's table, which is an interpretation of Berlekamp's iterative algorithm. The error location numbers are calculated by using the Chien search. Finally, the error values are computed by using Forney's method

    Error control for reliable digital data transmission and storage systems

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    A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code

    Decoding of Interleaved Reed-Solomon Codes Using Improved Power Decoding

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    We propose a new partial decoding algorithm for mm-interleaved Reed--Solomon (IRS) codes that can decode, with high probability, a random error of relative weight 1Rmm+11-R^{\frac{m}{m+1}} at all code rates RR, in time polynomial in the code length nn. For m>2m>2, this is an asymptotic improvement over the previous state-of-the-art for all rates, and the first improvement for R>1/3R>1/3 in the last 2020 years. The method combines collaborative decoding of IRS codes with power decoding up to the Johnson radius.Comment: 5 pages, accepted at IEEE International Symposium on Information Theory 201

    On the error statistics of Viterbi decoding and the performance of concatenated codes

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    Computer simulation results are presented on the performance of convolutional codes of constraint lengths 7 and 10 concatenated with the (255, 223) Reed-Solomon code (a proposed NASA standard). These results indicate that as much as 0.8 dB can be gained by concatenating this Reed-Solomon code with a (10, 1/3) convolutional code, instead of the (7, 1/2) code currently used by the DSN. A mathematical model of Viterbi decoder burst-error statistics is developed and is validated through additional computer simulations
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