Underdetermined-order recursive least-squares adaptive filtering: The concept and algorithms

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Adaptive Interference Mitigation in GPS Receivers

Satellite navigation systems (GNSS) are among the most complex radio-navigation systems, providing positioning, navigation, and timing (PNT) information. A growing number of public sector and commercial applications rely on the GNSS PNT service to support business growth, technical development, and the day-to-day operation of technology and socioeconomic systems. As GNSS signals have inherent limitations, they are highly vulnerable to intentional and unintentional interference. GNSS signals have spectral power densities far below ambient thermal noise. Consequently, GNSS receivers must meet high standards of reliability and integrity to be used within a broad spectrum of applications. GNSS receivers must employ effective interference mitigation techniques to ensure robust, accurate, and reliable PNT service. This research aims to evaluate the effectiveness of the Adaptive Notch Filter (ANF), a precorrelation mitigation technique that can be used to excise Continuous Wave Interference (CWI), hop-frequency and chirp-type interferences from GPS L1 signals. To mitigate unwanted interference, state-of-the-art ANFs typically adjust a single parameter, the notch centre frequency, and zeros are constrained extremely close to unity. Because of this, the notch centre frequency converges slowly to the target frequency. During this slow converge period, interference leaks into the acquisition block, thus sabotaging the operation of the acquisition block. Furthermore, if the CWI continuously hops within the GPS L1 in-band region, the subsequent interference frequency is locked onto after a delay, which means constant interference occurs in the receiver throughout the delay period. This research contributes to the field of interference mitigation at GNSS's receiver end using adaptive signal processing, predominately for GPS. This research can be divided into three stages. I first designed, modelled and developed a Simulink-based GPS L1 signal simulator, providing a homogenous test signal for existing and proposed interference mitigation algorithms. Simulink-based GPS L1 signal simulator provided great flexibility to change various parameters to generate GPS L1 signal under different conditions, e.g. Doppler Shift, code phase delay and amount of propagation degradation. Furthermore, I modelled three acquisition schemes for GPS signals and tested GPS L1 signals acquisition via coherent and non-coherent integration methods. As a next step, I modelled different types of interference signals precisely and implemented and evaluated existing adaptive notch filters in MATLAB in terms of Carrier to Noise Density (\u1d436/\u1d4410), Signal to Noise Ratio (SNR), Peak Degradation Metric, and Mean Square Error (MSE) at the output of the acquisition module in order to create benchmarks. Finally, I designed, developed and implemented a novel algorithm that simultaneously adapts both coefficients in lattice-based ANF. Mathematically, I derived the full-gradient term for the notch's bandwidth parameter adaptation and developed a framework for simultaneously adapting both coefficients of a lattice-based adaptive notch filter. I evaluated the performance of existing and proposed interference mitigation techniques under different types of interference signals. Moreover, I critically analysed different internal signals within the ANF structure in order to develop a new threshold parameter that resets the notch bandwidth at the start of each subsequent interference frequency. As a result, I further reduce the complexity of the structural implementation of lattice-based ANF, allowing for efficient hardware realisation and lower computational costs. It is concluded from extensive simulation results that the proposed fully adaptive lattice-based provides better interference mitigation performance and superior convergence properties to target frequency compared to traditional ANF algorithms. It is demonstrated that by employing the proposed algorithm, a receiver is able to operate with a higher dynamic range of JNR than is possible with existing methods. This research also presents the design and MATLAB implementation of a parameterisable Complex Adaptive Notch Filer (CANF). Present analysis on higher order CANF for detecting and mitigating various types of interference for complex baseband GPS L1 signals. In the end, further research was conducted to suppress interference in the GPS L1 signal by exploiting autocorrelation properties and discarding some portion of the main lobe of the GPS L1 signal. It is shown that by removing 30% spectrum of the main lobe, either from left, right, or centre, the GPS L1 signal is still acquirable

Genetic algorithms for designing digital filters

This thesis presents a method of adapting IIR filters implemented as lattice structures using a Genetic Algorithm (GA), called ZGA. This method addresses some of the difficulties encountered with existing methods of adaptation, providing guaranteed filter stability and the ability to search multi-modal error surfaces. ZGA mainly focuses on convergence improvement in respects of crossover and mutation operators. Four kinds of crossover methods are used to scan as much as possible the potential solution area, only the best of them will be taken as ZGA crossover offspring. And ZGA mutation takes the best of three mutation results as final mutation offspring. Simulation results are presented, demonstrating the suitability of ZGA to the problem of IIR system identification and comparing with the results of Standard GA, Genitor and NGA

The design and implementation of a microprocessor controlled adaptive filter

This thesis describes the construction and implementation of a microprocessor controlled recursive adaptive filter applied as a noise canceller. It describes the concept of the adaptive noise canceller, a method of estimating the received signal corrupted with additive interference (noise). This canceller has two inputs, the primary input containing the corrupted signal and the reference input consisting of the additive noise correlated in some unknown way to the primary noise. The reference input is filtered and subtracted from the primary input without degrading the desired components of the signal. This filtering process is adaptive and based on Widrow-Hoff Least-Mean-Square algorithm. Adaptive filters are programmable and have the capability to adjust their own parameters in situations where minimum piori knowledge is available about the inputs. For recursive filters, these parameters include feed-forward (non-recursive) as well as feedback (recursive) coefficients. A new design and implementation of the adaptive filter is suggested which uses a high speed 68000 microprocessor to accomplish the coefficients updating operation. Many practical problems arising in the hardware implementation are investigated. Simulation results illustrate the ability of the adaptive noise canceller to have an acceptable performance when the coefficients updating operation is carried out once every N sampling periods. Both simulation and hardware experimental results are in agreement

Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

Design of a reusable distributed arithmetic filter and its application to the affine projection algorithm

Digital signal processing (DSP) is widely used in many applications spanning the spectrum from audio processing to image and video processing to radar and sonar processing. At the core of digital signal processing applications is the digital filter which are implemented in two ways, using either finite impulse response (FIR) filters or infinite impulse response (IIR) filters. The primary difference between FIR and IIR is that for FIR filters, the output is dependent only on the inputs, while for IIR filters the output is dependent on the inputs and the previous outputs. FIR filters also do not sur from stability issues stemming from the feedback of the output to the input that aect IIR filters. In this thesis, an architecture for FIR filtering based on distributed arithmetic is presented. The proposed architecture has the ability to implement large FIR filters using minimal hardware and at the same time is able to complete the FIR filtering operation in minimal amount of time and delay when compared to typical FIR filter implementations. The proposed architecture is then used to implement the fast affine projection adaptive algorithm, an algorithm that is typically used with large filter sizes. The fast affine projection algorithm has a high computational burden that limits the throughput, which in turn restricts the number of applications. However, using the proposed FIR filtering architecture, the limitations on throughput are removed. The implementation of the fast affine projection adaptive algorithm using distributed arithmetic is unique to this thesis. The constructed adaptive filter shares all the benefits of the proposed FIR filter: low hardware requirements, high speed, and minimal delay.Ph.D.Committee Chair: Anderson, Dr. David V.; Committee Member: Hasler, Dr. Paul E.; Committee Member: Mooney, Dr. Vincent J.; Committee Member: Taylor, Dr. David G.; Committee Member: Vuduc, Dr. Richar

Low Power Digital Filter Implementation in FPGA

Digital filters suitable for hearing aid application on low power perspective have been developed and implemented in FPGA in this dissertation. Hearing aids are primarily meant for improving hearing and speech comprehensions. Digital hearing aids score over their analog counterparts. This happens as digital hearing aids provide flexible gain besides facilitating feedback reduction and noise elimination. Recent advances in DSP and Microelectronics have led to the development of superior digital hearing aids. Many researchers have investigated several algorithms suitable for hearing aid application that demands low noise, feedback cancellation, echo cancellation, etc., however the toughest challenge is the implementation. Furthermore, the additional constraints are power and area. The device must consume as minimum power as possible to support extended battery life and should be as small as possible for increased portability. In this thesis we have made an attempt to investigate possible digital filter algorithms those are hardware configurable on low power view point. Suitability of decimation filter for hearing aid application is investigated. In this dissertation decimation filter is implemented using ‘Distributed Arithmetic’ approach.While designing this filter, it is observed that, comb-half band FIR-FIR filter design uses less hardware compared to the comb-FIR-FIR filter design. The power consumption is also less in case of comb-half band FIR-FIR filter design compared to the comb-FIR-FIR filter. This filter is implemented in Virtex-II pro board from Xilinx and the resource estimator from the system generator is used to estimate the resources. However ‘Distributed Arithmetic’ is highly serial in nature and its latency is high; power consumption found is not very low in this type of filter implementation. So we have proceeded for ‘Adaptive Hearing Aid’ using Booth-Wallace tree multiplier. This algorithm is also implemented in FPGA and power calculation of the whole system is done using Xilinx Xpower analyser. It is observed that power consumed by the hearing aid with Booth-Wallace tree multiplier is less than the hearing aid using Booth multiplier (about 25%). So we can conclude that the hearing aid using Booth-Wallace tree multiplier consumes less power comparatively. The above two approached are purely algorithmic approach. Next we proceed to combine circuit level VLSI design and with algorithmic approach for further possible reduction in power. A MAC based FDF-FIR filter (algorithm) that uses dual edge triggered latch (DET) (circuit) is used for hearing aid device. It is observed that DET based MAC FIR filter consumes less power than the traditional (single edge triggered, SET) one (about 41%). The proposed low power latch provides a power saving upto 65% in the FIR filter. This technique consumes less power compared to previous approaches that uses low power technique only at algorithmic abstraction level. The DET based MAC FIR filter is tested for real-time validation and it is observed that it works perfectly for various signals (speech, music, voice with music). The gain of the filter is tested and is found to be 27 dB (maximum) that matches with most of the hearing aid (manufacturer’s) specifications. Hence it can be concluded that FDF FIR digital filter in conjunction with low power latch is a strong candidate for hearing aid application

Adaptive Control of Woofer-Tweeter Adaptive Optics

Adaptive optics applies advanced sensing and control to improve the ability of optical systems to collect images through a turbulent atmosphere. The results of this research effort demonstrate that the combination of two recent approaches improves the performance of adaptive optics in directed energy and laser communication scenarios. The first approach is adaptive control, which offers improved performance over fixed-gain controllers in the presence of rapidly changing turbulence. The second approach incorporated into the study is a dual-mirror system. The two mirrors are a high-bandwidth, low-actuator-stroke (tweeter) mirror and a low-bandwidth, large actuator-stroke (woofer) mirror. The woofer-tweeter combination allows for better compensation of the large-variance, high-spatial-frequency phase distortion generated by strong turbulence. Two different adaptive controllers are presented, one using a relatively simple model reference adaptive system controller and one using a lattice filter controller. The lattice filter is implemented in two ways. In one implementation the filter operates on the individual actuators, while in the other it operates on frequency weighted modes. The modal implementation reduces the computational burden of the filter. The performance of the different adaptive controllers is compared to both each other and to a traditional fixed-gain controller. Simulations show that adaptive control of woofer-tweeter AO can increase the mean Strehl ratio by up to 20%. In general, the lattice filter controllers outperform the model reference adaptive system controller. However, in cases where the lattice filter cannot use a sufficient number of modes, the model reference adaptive system can outperform the lattice filter