Fully-passive switched-capacitor techniques for high performance SAR ADC design

In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques. CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 µm process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channel’s Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step. This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional ∆Σ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 µm process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin

Improved Random Demodulator for Compressed Sensing Applications

The advances in the field of signal processing have led to the continuous increase in the bandwidth of signals. Sampling these signals becomes harder and harder due to the increased bandwidth. This brings in need for a complex high rate ADCs to meet the Nyquist rate which is the minimum rate to avoid aliasing. For a given increase in bandwidth, there has to be a corresponding increase in the sampling rate of ADC. This might not be possible in the near future at the current rate of increase in bandwidth. Hence, there is a need to replace the current Nyquist rate sampling method by a process that relaxes the requirements but still keeps the quality of signal reconstruction good . Compressed sensing is a new technique in the field of signal acquisition. Compressed sensing allows a signal to be acquired below Nyquist rate if the signal is sparse in a given domain. Compressed sensing makes possible to acquire sparse signals at rates below Nyquist rate. Signals like audio and images are sparse and can be sampled at a rate below the Nyquist rate. The random demodulator (RD) is a hardware architecture that is used to implement compressed sensing. A direct implementation of compressed sensing in hardware requires several copies of the RD. To reduce the complexity fewer RDs can be used. Usage of fewer RDs comes at the cost of decreased signal reconstruction performance. The contribution of this thesis is about improving the efficiency of RD. First contribution of this thesis involves proposing a new RD architecture that improves signal reconstruction quality using a post-acquisition randomization step. The second contribution of this thesis is to develop a hardware platform for compressed sensing using field programmable analog arrays (FPAAs) and field programmable gate arrays (FPGAs). This platform can be used to test new architectures of RD in hardware

Smart Sensor Networks For Sensor-Neural Interface

One in every fifty Americans suffers from paralysis, and approximately 23% of paralysis cases are caused by spinal cord injury. To help the spinal cord injured gain functionality of their paralyzed or lost body parts, a sensor-neural-actuator system is commonly used. The system includes: 1) sensor nodes, 2) a central control unit, 3) the neural-computer interface and 4) actuators. This thesis focuses on a sensor-neural interface and presents the research related to circuits for the sensor-neural interface. In Chapter 2, three sensor designs are discussed, including a compressive sampling image sensor, an optical force sensor and a passive scattering force sensor. Chapter 3 discusses the design of the analog front-end circuit for the wireless sensor network system. A low-noise low-power analog front-end circuit in 0.5μm CMOS technology, a 12-bit 1MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18μm CMOS process and a 6-bit asynchronous level-crossing ADC realized in 0.18μm CMOS process are presented. Chapter 4 shows the design of a low-power impulse-radio ultra-wide-band (IR-UWB) transceiver (TRx) that operates at a data rate of up to 10Mbps, with a power consumption of 4.9pJ/bit transmitted for the transmitter and 1.12nJ/bit received for the receiver. In Chapter 5, a wireless fully event-driven electrogoniometer is presented. The electrogoniometer is implemented using a pair of ultra-wide band (UWB) wireless smart sensor nodes interfacing with low power 3-axis accelerometers. The two smart sensor nodes are configured into a master node and a slave node, respectively. An experimental scenario data analysis shows higher than 90% reduction of the total data throughput using the proposed fully event-driven electrogoniometer to measure joint angle movements when compared with a synchronous Nyquist-rate sampling system. The main contribution of this thesis includes: 1) the sensor designs that emphasize power efficiency and data throughput efficiency; 2) the fully event-driven wireless sensor network system design that minimizes data throughput and optimizes power consumption

Communication channel analysis and real time compressed sensing for high density neural recording devices

Next generation neural recording and Brain- Machine Interface (BMI) devices call for high density or distributed systems with more than 1000 recording sites. As the recording site density grows, the device generates data on the scale of several hundred megabits per second (Mbps). Transmitting such large amounts of data induces significant power consumption and heat dissipation for the implanted electronics. Facing these constraints, efficient on-chip compression techniques become essential to the reduction of implanted systems power consumption. This paper analyzes the communication channel constraints for high density neural recording devices. This paper then quantifies the improvement on communication channel using efficient on-chip compression methods. Finally, This paper describes a Compressed Sensing (CS) based system that can reduce the data rate by > 10x times while using power on the order of a few hundred nW per recording channel

Low power data acquisition for microImplant biometric monitoring of tremors

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 97-100).In recent years, trends in the medical industry have created a growing demand for implantable medical devices. In particular, the need to provide doctors a means to continuously monitor biometrics over long time scales with increased precision is paramount to efficient healthcare. To make medical implants more attractive, there is a need to reduce their size and power consumption. Small medical implants would allow for less invasive procedures, greater comfort for patients, and increased patient compliance. Reductions in power consumption translate to longer battery life. The two primary limitations to the size of small medical implants are the batteries that provide energy to circuit and sensor components and the antennas that enable wireless communication to terminals outside of the body. The theory is applied in the context of the long term monitoring of Parkinson's tremors. This work investigates how to reduce the amount of data needing to acquire a signal by applying compressive sampling thereby alleviating the demand on the energy source. A low energy SAR ADC is designed using adiabatic charging to further reduce energy usage. This application is ideal for adiabatic techniques because of the low frequency of operation and the ease with which we can reclaim energy from discharging the capacitors. Keywords: SAR ADC, adiabatic, compressive sampling, biometric, implantsby Tania Khanna.Ph.D

Image compression and energy harvesting for energy constrained sensors

Title from PDF of title page, viewed on June 21, 2013Dissertation advisor: Walter D. Leon-SalasVitaIncludes bibliographic references (pages 176-[187])Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2013The advances in complementary metal-oxide-semiconductor (CMOS) technology have led to the integration of all components of electronic system into a single integrated circuit. Ultra-low power circuit techniques have reduced the power consumption of circuits. Moreover, solar cells with improved efficiency can be integrated on chip to harvest energy from sunlight. As a result of all the above, a new class of miniaturized electronic systems known as self-powered system on a chip has emerged. There is an increasing research interest in the area of self-powered devices which provide cost-effective solutions especially when these devices are used in the areas that changing or replacing batteries is too costly. Therefore, image compression and energy harvesting are studied in this dissertation. The integration of energy harvesting, image compression, and an image sensor on the same chip provides the energy source to charge a battery, reduces the data rate, and improves the performance of wireless image sensors. Integrated circuits of image compression, solar energy harvesting, and image sensors are studied, designed, and analyzed in this work. In this dissertation, a hybrid image sensor that can perform the tasks of sensing and energy harvesting is presented. Photodiodes of hybrid image sensor can be programmed as image sensors or energy harvesting cells. The hybrid image sensor can harvest energy in between frames, in sleep mode, and even when it is taking images. When sensing images and harvesting energy are both needed at the same time, some pixels have to work as sensing pixels, and the others have to work as solar cells. Since some pixels are devoted to harvest energy, the resolution of the image will be reduced. To preserve the resolution or to keep the fair resolution when a lot of energy collection is needed, image reconstruction algorithms and compressive sensing theory provide solutions to achieve a good image quality. On the other hand, when the battery has enough charge, image compression comes into the picture. Multiresolution decomposition image compression provides a way to compress image data in order to reduce the energy need from data transmission. The solution provided in this dissertation not only harvests energy but also saves energy resulting long lasting wireless sensors. The problem was first studied at the system level to identify the best system-level configuration which was then implemented on silicon. As a proof of concept, a 32 x 32 array of hybrid image sensor, a 32 x 32 array of image sensor with multiresolution decomposition compression, and a compressive sensing converter have been designed and fabricated in a standard 0.5 [micrometer] CMOS process. Printed circuit broads also have been designed to test and verify the proposed and fabricated chips. VHDL and Matlab codes were written to generate the proper signals to control, and read out data from chips. Image processing and recovery were carried out in Matlab. DC-DC converters were designed to boost the inherently low voltage output of the photodiodes. The DC-DC converter has also been improved to increase the efficiency of power transformation.Introduction -- Hybrid imager system and circuit design -- Hybrid imager energy harvesting and image acquisition results and discussion -- Detailed description and mathematical analysis for a circuit of energy harvesting using on-chip solar cells -- Multiresolution decomposition for lossless and near-lossless compression -- An incremental [sigma-delta] converter for compressive sensing -- Detailed description of a sigma-delta random demodulator converter architecture for compressive sensing applications -- Conclusion -- Appendix A. Chip pin-out -- Appendix B. Schematics -- Appendix C. Pictures of custom PC

Compressive Sensing with Low-Power Transfer and Accurate Reconstruction of EEG Signals

Tele-monitoring of EEG in WBAN is essential as EEG is the most powerful physiological parameters to diagnose any neurological disorder. Generally, EEG signal needs to record for longer periods which results in a large volume of data leading to huge storage and communication bandwidth requirements in WBAN. Moreover, WBAN sensor nodes are battery operated which consumes lots of energy. The aim of this research is, therefore, low power transmission of EEG signal over WBAN and its accurate reconstruction at the receiver to enable continuous online-monitoring of EEG and real time feedback to the patients from the medical experts. To reduce data rate and consequently reduce power consumption, compressive sensing (CS) may be employed prior to transmission. Nonetheless, for EEG signals, the accuracy of reconstruction of the signal with CS depends on a suitable dictionary in which the signal is sparse. As the EEG signal is not sparse in either time or frequency domain, identifying an appropriate dictionary is paramount. There are a plethora of choices for the dictionary to be used. Wavelet bases are of interest due to the availability of associated systems and methods. However, the attributes of wavelet bases that can lead to good quality of reconstruction are not well understood. For the first time in this study, it is demonstrated that in selecting wavelet dictionaries, the incoherence with the sensing matrix and the number of vanishing moments of the dictionary should be considered at the same time. In this research, a framework is proposed for the selection of an appropriate wavelet dictionary for EEG signal which is used in tandem with sparse binary matrix (SBM) as the sensing matrix and ST-SBL method as the reconstruction algorithm. Beylkin (highly incoherent with SBM and relatively high number of vanishing moments) is identified as the best dictionary to be used amongst the dictionaries are evaluated in this thesis. The power requirements for the proposed framework are also quantified using a power model. The outcomes will assist to realize the computational complexity and online implementation requirements of CS for transmitting EEG in WBAN. The proposed approach facilitates the energy savings budget well into the microwatts range, ensuring a significant savings of battery life and overall system’s power. The study is intended to create a strong base for the use of EEG in the high-accuracy and low-power based biomedical applications in WBAN

Learning-Based Hardware Design for Data Acquisition Systems

This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path

A HIGHLY-SCALABLE DC-COUPLED DIRECT-ADC NEURAL RECORDING CHANNEL ARCHITECTURE WITH INPUT-ADAPTIVE RESOLUTION

This thesis presents the design, development, and characterization of a novel neural recording channel architecture with (a) quantization resolution that is adaptive to the input signal's level of activity, (b) fully-dynamic power consumption that is linearly proportional to the recording resolution, and (c) immunity to DC offset and drifts at the input. Our results demonstrate the proposed design's capability in conducting neural recording with near lossless input-adaptive data compression, leading to a significant reduction in the energy required for both recording and data transmission, hence allowing for a potential high scaling of the number of recording channels integrated on a single implanted microchip without the need to increase the power budget. The proposed channel with the implemented compression technique is implemented in a standard 130nm CMOS technology with overall power consumption of 7.6uW and active area of 92×92µm for the implemented digital-backend