Can my chip behave like my brain?

Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D

Scalable parallel architecture for biological neural simulation on hardware platforms

Difficulties and dangers in doing experiments on living systems and providing a testbed for theorists make the biologically detailed neural simulation an essential part of neurobiology. Due to the complexity of the neural systems and dynamic properties of the neurons simulation of biologically realistic models is very challenging area. Currently all general purpose simulator are software based. Limitation on the available processing power provides a huge gap between the maximum practical simulation size and human brain simulation as the most complex neural system. This thesis aimed at providing a hardware friendly parallel architecture in order to accelerate the simulation process. This thesis presents a scalable hierarchical architecture for accelerating simulations of large-scale biological neural systems on field-programmable gate arrays (FPGAs). The architecture provides a high degree of flexibility to optimize the parallelization ratio based on available hardware resources and model specifications such as complexity of dendritic trees. The whole design is based on three types of customized processors and a switching module. An addressing scheme is developed which allows flexible integration of various combination of processors. The proposed addressing scheme, design modularity and data process localization allow the whole system to extend over multiple FPGA platforms to simulate a very large biological neural system. In this research Hodgkin-Huxley model is adopted for cell excitability. Passive compartmental approach is used to model dendritic tree with any level of complexity. The whole architecture is verified in MATLAB and all processor modules and the switching unit implemented in Verilog HDL and Schematic Capture. A prototype simulator is integrated and synthesized for Xilinx V5-330t-1 as the target FPGA. While not dependent on particular IP (Intellectual Property) cores, the whole implementation is based on Xilinx IP cores including IEEE-754 64-bit floating-point adder and multiplier cores. The synthesize results and performance analyses are provided

Digital neural circuits : from ions to networks

PhD ThesisThe biological neural computational mechanism is always fascinating to human beings since it shows several state-of-the-art characteristics: strong fault tolerance, high power efficiency and self-learning capability. These behaviours lead the developing trend of designing the next-generation digital computation platform. Thus investigating and understanding how the neurons talk with each other is the key to replicating these calculation features. In this work I emphasize using tailor-designed digital circuits for exactly implementing bio-realistic neural network behaviours, which can be considered a novel approach to cognitive neural computation. The first advance is that biological real-time computing performances allow the presented circuits to be readily adapted for real-time closed-loop in vitro or in vivo experiments, and the second one is a transistor-based circuit that can be directly translated into an impalpable chip for high-level neurologic disorder rehabilitations. In terms of the methodology, first I focus on designing a heterogeneous or multiple-layer-based architecture for reproducing the finest neuron activities both in voltage-and calcium-dependent ion channels. In particular, a digital optoelectronic neuron is developed as a case study. Second, I focus on designing a network-on-chip architecture for implementing a very large-scale neural network (e.g. more than 100,000) with human cognitive functions (e.g. timing control mechanism). Finally, I present a reliable hybrid bio-silicon closed-loop system for central pattern generator prosthetics, which can be considered as a framework for digital neural circuit-based neuro-prosthesis implications. At the end, I present the general digital neural circuit design principles and the long-term social impacts of the presented work

Double-Floating-Gate van der Waals Transistor for High-Precision Synaptic Operations

Department of Materials Science and EngineeringTwo-dimensional materials and their heterostructures have thus far been identified as leading candidates for nanoelectronics owing to the near-atom thickness, superior electrostatic control, and adjustable device architecture. These characteristics are indeed advantageous for neuro-inspired computing hardware where the precise programming is strongly required. However, its successful demonstration fully utilizing all of the given benefits remains to be further developed. Herein, we present van der Waals (vdW) integrated synaptic transistors with multi-stacked floating gates, which are reconfigured upon surface oxidation. When compared with a conventional device structure with a single floating gate, our double-floating-gate (DFG) device exhibits better non-volatile memory performance, including a large memory window (100 V), high on???off current ratio (107), relatively long retention time (5000 s), and satisfactory cyclic endurance (500 cycles), all of which can be attributed to its increased chargestorage capacity and spatial redistribution. This facilitates highly effective modulation of trapped charge density with a large dynamic range. Consequently, the DFG transistor exhibits an improved weight update profile in long-term potentiation/depression synaptic behavior for nearly ideal classification accuracies of up to 96.12% (MNIST) and 81.68% (Fashion-MNIST). Our work adds a powerful option to vdW-bonded device structures for highly efficient neuromorphic computing.ope

Development of a Multi-Compartment Neuron Model Emulation

This work describes the design of an analog circuit emulating a multi-compartment neuron model on a microchip. Initially, the single-compartment adaptive exponential integrate-and-fire neuron model is implemented as a hardware model. Therefor, the differential equations describing the model dynamics are directly translated into an electronic circuit based on operational transconductance amplifiers. Consequently a close correspondence between model and circuit is achieved enabling references to experiments done with computer simulators. 512 of these neurons are implemented on a single micro-chip. Individual control of each neuron’s biases is achieved by the use of analog floating-gate memory. In most cases, these biases directly correspondent to parameters of the model, hence simple translations are possible. The single neuron implementation has been verified on a prototype chip in several experiments. Inter alia, its capabilities of reproducing biological neuron’s behavior and the influence of fixed-pattern noise on the circuit are analyzed. To step over to a multi-compartment circuit, the neuron has been enhanced by a resistive element and a routing network to build complex dendrite structures. Furthermore, the parameterization allows compartments of different sizes covering large somatic and small dendritic compartments. A dedicated test chip has been designed for the verification of the new model. Several simulations show the enhanced behavior of the multi-compartment emulation including dendritic attenuation and active spike propagation. The neuron circuits are dedicated for a new kind of computer based on the cortex

A Practical Investigation into Achieving Bio-Plausibility in Evo-Devo Neural Microcircuits Feasible in an FPGA

Many researchers has conjectured, argued, or in some cases demonstrated, that bio-plausibility can bring about emergent properties such as adaptability, scalability, fault-tolerance, self-repair, reliability, and autonomy to bio-inspired intelligent systems. Evolutionary-developmental (evo-devo) spiking neural networks are a very bio-plausible mixture of such bio-inspired intelligent systems that have been proposed and studied by a few researchers. However, the general trend is that the complexity and thus the computational cost grow with the bio-plausibility of the system. FPGAs (Field- Programmable Gate Arrays) have been used and proved to be one of the flexible and cost efficient hardware platforms for research' and development of such evo-devo systems. However, mapping a bio-plausible evo-devo spiking neural network to an FPGA is a daunting task full of different constraints and trade-offs that makes it, if not infeasible, very challenging. This thesis explores the challenges, trade-offs, constraints, practical issues, and some possible approaches in achieving bio-plausibility in creating evolutionary developmental spiking neural microcircuits in an FPGA through a practical investigation along with a series of case studies. In this study, the system performance, cost, reliability, scalability, availability, and design and testing time and complexity are defined as measures for feasibility of a system and structural accuracy and consistency with the current knowledge in biology as measures for bio-plausibility. Investigation of the challenges starts with the hardware platform selection and then neuron, cortex, and evo-devo models and integration of these models into a whole bio-inspired intelligent system are examined one by one. For further practical investigation, a new PLAQIF Digital Neuron model, a novel Cortex model, and a new multicellular LGRN evo-devo model are designed, implemented and tested as case studies. Results and their implications for the researchers, designers of such systems, and FPGA manufacturers are discussed and concluded in form of general trends, trade-offs, suggestions, and recommendations