Wavelength-multiplexed duplex transceiver based on III-V/Si hybrid integration for off-chip and on-chip optical interconnects

A six-channel wavelength-division-multiplexed optical transceiver with a compact footprint of 1.5 x 0.65 mm(2) for off-chip and on-chip interconnects is demonstrated on a single silicon-on-insulator chip. An arrayed waveguide grating is used as the (de)multiplexer, and III-V electroabsorption sections fabricated by hybrid integration technology are used as both modulators and detectors, which also enable duplex links. The 30-Gb/s capacity for each of the six wavelength channels for the off-chip transceiver is demonstrated. For the on-chip interconnect, an electrical-to-electrical 3-dB bandwidth of 13 GHz and a data rate of 30 Gb/s per wavelength are achieved

An Energy-Efficient Reconfigurable Mobile Memory Interface for Computing Systems

The critical need for higher power efficiency and bandwidth transceiver design has significantly increased as mobile devices, such as smart phones, laptops, tablets, and ultra-portable personal digital assistants continue to be constructed using heterogeneous intellectual properties such as central processing units (CPUs), graphics processing units (GPUs), digital signal processors, dynamic random-access memories (DRAMs), sensors, and graphics/image processing units and to have enhanced graphic computing and video processing capabilities. However, the current mobile interface technologies which support CPU to memory communication (e.g. baseband-only signaling) have critical limitations, particularly super-linear energy consumption, limited bandwidth, and non-reconfigurable data access. As a consequence, there is a critical need to improve both energy efficiency and bandwidth for future mobile devices.;The primary goal of this study is to design an energy-efficient reconfigurable mobile memory interface for mobile computing systems in order to dramatically enhance the circuit and system bandwidth and power efficiency. The proposed energy efficient mobile memory interface which utilizes an advanced base-band (BB) signaling and a RF-band signaling is capable of simultaneous bi-directional communication and reconfigurable data access. It also increases power efficiency and bandwidth between mobile CPUs and memory subsystems on a single-ended shared transmission line. Moreover, due to multiple data communication on a single-ended shared transmission line, the number of transmission lines between mobile CPU and memories is considerably reduced, resulting in significant technological innovations, (e.g. more compact devices and low cost packaging to mobile communication interface) and establishing the principles and feasibility of technologies for future mobile system applications. The operation and performance of the proposed transceiver are analyzed and its circuit implementation is discussed in details. A chip prototype of the transceiver was implemented in a 65nm CMOS process technology. In the measurement, the transceiver exhibits higher aggregate data throughput and better energy efficiency compared to prior works

Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

Ultra-Wide-Band (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB System-on-Chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging metho

High-performance wireless power and data transfer interface for implantable medical devices

D’importants progès ont été réalisés dans le développement des systèmes biomédicaux implantables grâce aux dernières avancées de la microélectronique et des technologies sans fil. Néanmoins, ces appareils restent difficiles à commercialier. Cette situation est due particulièrement à un manque de stratégies de design capable supporter les fonctionnalités exigées, aux limites de miniaturisation, ainsi qu’au manque d’interface sans fil à haut débit fiable et faible puissance capable de connecter les implants et les périphériques externes. Le nombre de sites de stimulation et/ou d’électrodes d’enregistrement retrouvés dans les dernières interfaces cerveau-ordinateur (IMC) ne cesse de croître afin d’augmenter la précision de contrôle, et d’améliorer notre compréhension des fonctions cérébrales. Ce nombre est appelé à atteindre un millier de site à court terme, ce qui exige des débits de données atteingnant facilement les 500 Mbps. Ceci étant dit, ces travaux visent à élaborer de nouvelles stratégies innovantes de conception de dispositifs biomédicaux implantables afin de repousser les limites mentionnées ci-dessus. On présente de nouvelles techniques faible puissance beaucoup plus performantes pour le transfert d’énergie et de données sans fil à haut débit ainsi que l’analyse et la réalisation de ces dernières grâce à des prototypes microélectroniques CMOS. Dans un premier temps, ces travaux exposent notre nouvelle structure multibobine inductive à résonance présentant une puissance sans fil distribuée uniformément pour alimenter des systèmes miniatures d’étude du cerveaux avec des models animaux en ilberté ainsi que des dispositifs médicaux implantbles sans fil qui se caractérisent par une capacité de positionnement libre. La structure propose un lien de résonance multibobines inductive, dont le résonateur principal est constitué d’une multitude de résonateurs identiques disposés dans une matrice de bobines carrées. Ces dernières sont connectées en parallèle afin de réaliser des surfaces de puissance (2D) ainsi qu’une chambre d’alimentation (3D). La chambre proposée utilise deux matrices de résonateurs de base, mises face à face et connectés en parallèle afin d’obtenir une distribution d’énergie uniforme en 3D. Chaque surface comprend neuf bobines superposées, connectées en parallèle et réailsées sur une carte de circuit imprimé deux couches FR4. La chambre dispose d’un mécanisme naturel de localisation de puissance qui facilite sa mise en oeuvre et son fonctionnement. En procédant ainsi, nous évitons la nécessité d’une détection active de l’emplacement de la charge et le contrôle d’alimentation. Notre approche permet à cette surface d’alimentation unique de fournir une efficacité de transfert de puissance (PTE) de 69% et une puissance délivrée à la charge (PDL) de 120 mW, pour une distance de séparation de 4 cm, tandis que le prototype de chambre complet fournit un PTE uniforme de 59% et un PDL de 100 mW en 3D, partout à l’intérieur de la chambre avec un volume de chambre de 27 × 27 × 16 cm3. Une étape critique avant d’utiliser un dispositif implantable chez les humains consiste à vérifier ses fonctionnalités sur des sujets animaux. Par conséquent, la chambre d’énergie sans fil conçue sera utilisée afin de caractériser les performances d’ une interface sans fil de transmisison de données dans un environnement réaliste in vivo avec positionement libre. Un émetteur-récepteur full-duplex (FDT) entièrement intégré qui se caractérise par sa faible puissance est conçu pour réaliser une interfaces bi-directionnelles (stimulation et enregistrement) avec des débits asymétriques: des taux de tramnsmission plus élevés sont nécessaires pour l’enregistrement électrophysiologique multicanal (signaux de liaison montante) alors que les taux moins élevés sont utilisés pour la stimulation (les signaux de liaison descendante). L’émetteur (TX) et le récepteur (RX) se partagent une seule antenne afin de réduire la taille de l’implant. L’émetteur utilise la radio ultra-large bande par impulsions (IR-UWB) basée sur l’approche edge combining et le RX utilise la bande ISM (Industrielle, Scientifique et Médicale) de fréquence central 2.4 GHz et la modulation on-off-keying (OOK). Une bonne isolation (> 20 dB) est obtenue entre le TX et le RX grâce à 1) la mise en forme les impulsions émises dans le spectre UWB non réglementée (3.1-7 GHz), et 2) le filtrage espace-efficace (évitant l’utilisation d’un circulateur ou d’un diplexeur) du spectre du lien de communication descendant directement au niveau de l’ amplificateur à faible bruit (LNA). L’émetteur UWB 3.1-7 GHz utilise un e modultion OOK ainsi qu’une modulation par déplacement de phase (BPSK) à seulement 10.8 pJ / bits. Le FDT proposé permet d’atteindre 500 Mbps de débit de données en lien montant et 100 Mbps de débit de données de lien descendant. Il est entièrement intégré dans un procédé TSMC CMOS 0.18 um standard et possède une taille totale de 0.8 mm2. La consommation totale d’énergie mesurée est de 10.4 mW (5 mW pour RX et 5.4 mW pour TX au taux de 500 Mbps).In recent years, there has been major progress on implantable biomedical systems that support most of the functionalities of wireless implantable devices. Nevertheless, these devices remain mostly restricted to be commercialized, in part due to weakness of a straightforward design to support the required functionalities, limitation on miniaturization, and lack of a reliable low-power high data rate interface between implants and external devices. This research provides novel strategies on the design of implantable biomedical devices that addresses these limitations by presenting analysis and techniques for wireless power transfer and efficient data transfer. The first part of this research includes our proposed novel resonance-based multicoil inductive power link structure with uniform power distribution to wirelessly power up smart animal research systems and implanted medical devices with high power efficiency and free positioning capability. The proposed structure consists of a multicoil resonance inductive link, which primary resonator array is made of several identical resonators enclosed in a scalable array of overlapping square coils that are connected in parallel and arranged in power surface (2D) and power chamber (3D) configurations. The proposed chamber uses two arrays of primary resonators, facing each other, and connected in parallel to achieve uniform power distribution in 3D. Each surface includes 9 overlapped coils connected in parallel and implemented into two layers of FR4 printed circuit board. The chamber features a natural power localization mechanism, which simplifies its implementation and eases its operation by avoiding the need for active detection of the load location and power control mechanisms. A single power surface based on the proposed approach can provide a power transfer efficiency (PTE) of 69% and a power delivered to the load (PDL) of 120 mW, for a separation distance of 4 cm, whereas the complete chamber prototype provides a uniform PTE of 59% and a PDL of 100 mW in 3D, everywhere inside the chamber with a chamber size of 27×27×16 cm3. The second part of this research includes our proposed novel, fully-integrated, low-power fullduplex transceiver (FDT) to support bi-directional neural interfacing applications (stimulating and recording) with asymmetric data rates: higher rates are required for recording (uplink signals) than stimulation (downlink signals). The transmitter (TX) and receiver (RX) share a single antenna to reduce implant size. The TX uses impulse radio ultra-wide band (IR-UWB) based on an edge combining approach, and the RX uses a novel 2.4-GHz on-off keying (OOK) receiver. Proper isolation (> 20 dB) between the TX and RX path is implemented 1) by shaping the transmitted pulses to fall within the unregulated UWB spectrum (3.1-7 GHz), and 2) by space-efficient filtering (avoiding a circulator or diplexer) of the downlink OOK spectrum in the RX low-noise amplifier (LNA). The UWB 3.1-7 GHz transmitter using OOK and binary phase shift keying (BPSK) modulations at only 10.8 pJ/bit. The proposed FDT provides dual band 500 Mbps TX uplink data rate and 100 Mbps RX downlink data rate. It is fully integrated on standard TSMC 0.18 nm CMOS within a total size of 0.8 mm2. The total power consumption measured 10.4 mW (5 mW for RX and 5.4 mW for TX at the rate of 500 Mbps)

Monolithic integrated reflective transceiver in indium phosphide

The work presented in this thesis is about an InP based monolithic integrated reflective transceiver meant for use in future fiber access networks at the user site. The motivation for this research results from the users’ demands for ever-increasing bandwidth at low cost of operation, administration and maintenance. We investigated solutions to these challenges with a network concept using a dynamically reconfigurable optical network topology with a wavelength router and a colorless optical network unit. This work focuses on developing the optical part of the optical network unit, a reflective transceiver. This reflective transceiver consists of three basic components: a tunable wavelength duplexer, a photodetector and a reflective modulator. The tunable wavelength duplexer separates two wavelengths, one for the downstream and one for the upstream signals, and guides them to the photodetector and the reflective modulator. The photodetector detects the downstream data. The reflective modulator modulates the light carrier with the upstream data and reflects it back to the network. The integrated transceiver was realized bymonolithically integrating these components on a common active-passive butt-joint layer stack based on InP technology. This approach not only offers high bandwidth for both downstream data and upstream data, but also lowers the cost of the device and the network operation because of the colorless operation at the user site. The main results obtained within this work are summarized as follows: an efficient and polarization insensitive tunable wavelength duplexer was realized; a new method to fabricate a reflective SOA has been proposed and demonstrated; a high performance waveguide photodetector based on SOA layer stack was successfully fabricated; a low cost photoreceiverwhich includes an InP photodetector and a SiGe amplifier was demonstrated; aworking monolithic integrated reflective transceiver based on InP was successfully realized and demonstrated; two monolithic integrated transceivers aiming for higher bandwidth have been designed and fabricated. In addition, a novel MMI reflector has been proposed and realized with high reflectivity. This work was funded by DutchMinistry of Economic Affairs through the Freeband Project Broadband Photonics Access, the Smartmix projectMemphis and the NRC Photonics

Radio hardware virtualization for software-defined wireless networks

Software-Defined Network (SDN) is a promising architecture for next generation Internet. SDN can achieve Network Function Virtualization much more efficiently than conventional architectures by splitting the data and control planes. Though SDN emerged first in wired network, its wireless counterpart Software-Defined Wireless Network (SDWN) also attracted an increasing amount of interest in the recent years. Wireless networks have some distinct characteristics compared to the wired networks due to the wireless channel dynamics. Therefore, network controllers present some extra degrees of freedom, such as taking measurements against interference and noise, or adapting channels according to the radio spectrum occupation. These specific characteristics bring about more challenges to wireless SDNs. Currently, SDWN implementations are mainly using customized firmware, such as OpenWRT, running on an embedded application processor in commercial WiFi chips, and restricted to layers above lower Media Access Control. This limitation comes from the fact that radio hardware usually require specific drivers, which have a proprietary implementation by various chipset vendors. Hence, it is difficult, if not impossible, to achieve virtualization on the radio hardware. However, this status has been changing as Software-Defined Radio (SDR) systems open up the entire radio communication stack to radio hobbyists and researchers. The bridge between SDR and SDN will make it possible to bring the softwarization and virtualization of wireless networks down to the physical layer, which will unlock the full potential of SDWN. This paper investigates the necessity and feasibility of extending the virtualization of wireless networks towards the radio hardware. A SDR architecture is presented for radio hardware virtualization in order to facilitate SDWN design and experimentation. We do believe that by adopting the virtualization-oriented hardware accelerator design presented here, an all-layer end-to-end high performance SDWN can be achieved

차세대 자동차용 카메라 데이터 통신을 위한 비대칭 동시 양방향 송수신기의 설계

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 정덕균.본 학위 논문에서는 차세대 자동차용 카메라 링크를 위해 높은 속도의 4레벨 펄스 진폭 변조 신호와 낮은 속도의 2레벨 펄스 진폭 변조 신호를 통신하는 비대칭 동시 양방향 송수신기의 설계 기술에 대해 제안하고 검증되었다. 첫번째 프로토타입 설계에서는, 10B6Q 직류 밸런스 코드를 탑재한 4레벨 펄스 진폭 변조 송신기와 고정된 데이터와 참조 레벨을 가지는 4레벨 펄스 진폭 변조 적응형 수신기에 대한 내용이 기술되었다. 4레벨 펄스 진폭 변조 송신기에서는 교류 연결 링크 시스템에 대응하기 위한 면적 및 전력 효율성이 좋은 10B6Q 코드가 제안되었다. 이 코드는 직류 밸런스를 맞추고 연속적으로 같은 심볼을 가지는 길이를 6개로 제한 시킨다. 비록 여기서는 입력 데이터 길이 10비트를 사용하였지만, 제안된 기술은 카메라의 다양한 데이터 타입에 대응할 수 있도록 입력 데이터 길이에 대한 확장성을 가진다. 반면, 4레벨 펄스 진폭 변조 적응형 수신기에서는, 샘플러의 옵셋을 최적으로 제거하여 더 낮은 비트에러율을 얻기 위해서, 기존의 데이터 및 참조 레벨을 조절하는 대신, 이 레벨들은 고정시키고 가변 게인 증폭기를 적응형으로 조절하도록 하였다. 상기 10B6Q 코드 및 고정 데이터 및 참조레벨 기술을 가진 프로토타입 칩들은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었고 칩 온 보드 형태로 평가되었다. 10B6Q 코드는 합성 게이트 숫자는 645개와 함께 단 0.0009 mm2 의 면적 만을 차지한다. 또한, 667 MHz 동작 주파수에서 단 0.23 mW 의 전력을 소모한다. 10B6Q 코드를 탑재한 송신기에서 8-Gb/s 4레벨 펄스 진폭 변조 신호를 고정 데이터 및 참조 레벨을 가지는 적응형 수신기로 12-m 케이블 (22-dB 채널 로스) 을 통해서 보낸 결과 최소 비트 에러율 108 을 달성하였고, 비트 에러율 105 에서는 아이 마진이 0.15 UI x 50 mV 보다 크게 측정되었다. 송수신기를 합친 전력 소모는 65.2 mW (PLL 제외) 이고, 성과의 대표수치는 0.37 pJ/b/dB 를 보여주었다. 첫번째 프로토타입 설계을 포함하여 개선된 두번째 프로토타입 설계에서는, 12-Gb/s 4레벨 펄스 진폭 변조 정방향 채널 신호와 125-Mb/s 2레벨 펄스 진폭 변조 역방향 채널 신호를 탑재한 비대칭 동시 양방향 송수신기에 대해 기술되고 검증되었다. 제안된 넓은 선형 범위를 가지는 하이브리드는 gmC 저대역 통과 필터와 에코 제거기와 함께 아웃바운드 신호를 24 dB 이상 효율적으로 감소시켰다. 또한, 넓은 선형 범위를 가지는 하이브리드와 함께 게인 감소기를 형성하게 되는 선형 범위 증폭기를 통해 4레벨 펄스 진폭 변조 신호의 선형성과 진폭의 트레이드 오프 관계를 깨는 것이 가능하였다. 동시 양방향 송수신기 칩은 40 나노미터 상호보완형 메탈 산화 반도체 공정으로 제작되었다. 상기 설계 기술들을 이용하여, 4레벨 펄스 진폭 변조 및 2레벨 펄스 진폭 변조 송수신기 모두 5m 채널 (채널 로스 15.9 dB) 에서 1E-12 보다 낮은 비트 에러율을 달성하였고, 총 78.4 mW 의 전력 소모를 기록하였다. 종합적인 송수신기는 성과 대표지표로 0.41 pJ/b/dB 와 함께 동시 양방향 통신 아래에서 4레벨 펄스 진폭 변조 신호 및 2레벨 펄스 진폭 변조 신호 각각에서 아이 마진 0.15 UI 와 0.57 UI 를 달성하였다. 이 수치는 성과 대표지표 0.5 이하를 가지는 기존 동시 양방향 송수신기와의 비교에서 최고의 아이 마진을 기록하였다.In this dissertation, design techniques of a highly asymmetric simultaneous bidirectional (SB) transceivers with high-speed PAM-4 and low-speed PAM-2 signals are proposed and demonstrated for the next-generation automotive camera link. In a first prototype design, a PAM-4 transmitter with 10B6Q DC balance code and a PAM-4 adaptive receiver with fixed data and threshold levels (dtLevs) are presented. In PAM-4 transmitter, an area- and power-efficient 10B6Q code for an AC coupled link system that guarantees DC balance and limited run length of six is proposed. Although the input data width of 10 bits is used here, the proposed scheme has an extensibility for the input data width to cover various data types of the camera. On the other hand, in the PAM-4 adaptive receiver, to optimally cancel the sampler offset for a lower BER, instead of adjusting dtLevs, the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The prototype chips including above proposed 10B6Q code and fixed dtLevs are fabricated in 40-nm CMOS technology and tested in chip-on-board assembly. The 10B6Q code only occupies an active area of 0.0009 mm2 with a synthesized gate count of 645. It also consumes 0.23 mW at the operating clock frequency of 667 MHz. The transmitter with 10B6Q code delivers 8-Gb/s PAM-4 signal to the adaptive receiver using fixed dtLevs through a lossy 12-m cable (22-dB channel loss) with a BER of 1E-8, and the eye margin larger than 0.15 UI x 50 mV is measured for a BER of 1E-5. The proto-type chips consume 65.2 mW (excluding PLL), exhibiting an FoM of 0.37 pJ/b/dB. In a second prototype design advanced from the first prototypes, An asymmetric SB transceivers incorporating a 12-Gb/s PAM-4 forward channel and a 125-Mb/s PAM-2 back channel are presented and demonstrated. The proposed wide linear range (WLR) hybrid combined with a gmC low-pass filter and an echo canceller effectively suppresses the outbound signals by more than 24dB. In addition, linear range enhancer which forms a gain attenuator with WLR hybrid breaks the trade-off between the linearity and the amplitude of the PAM-4 signal. The SB transceiver chips are separately fabricated in 40-nm CMOS technology. Using above design techniques, both PAM-4 and PAM-2 SB transceivers achieve BER less than 1E-12 over a 5-m channel (15.9 dB channel loss), consuming 78.4 mW. The overall transceivers achieve an FoM of 0.41 pJ/b/dB and eye margin (at BER of 1E-12) of 0.15 UI and 0.57 UI for the forward PAM-4 and back PAM-2 signals, respectively, under SB communication. This is the best eye margin compared to the prior art SB transceivers with an FoM less than 0.5.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 DISSERTATION ORGANIZATION 4 CHAPTER 2 BACKGROUND ON AUTOMOTIVE CAMERA LINK 6 2.1 OVERVIEW 6 2.2 SYSTEM REQUIREMENTS 10 2.2.1 CHANNEL 10 2.2.2 POWER OVER DIFFERENTIAL LINE (PODL) 12 2.2.3 AC COUPLING AND DC BALANCE CODE 15 2.2.4 SIMULTANEOUS BIDIRECTIONAL COMMUNICATION 18 2.2.4.1 HYBRID 18 2.2.4.2 ECHO CANCELLER 20 2.2.5 ADAPTIVE RECEIVE EQUALIZATION 22 CHAPTER 3 AREA AND POWER EFFICIENT 10B6Q ENCODER FOR DC BALANCE 25 3.1 INTRODUCTION 25 3.2 PRIOR WORKS 28 3.3 PROPOSED AREA- AND POWER-EFFICIENT 10B6Q PAM-4 CODER 30 3.4 DESIGN OF THE 10B6Q CODE 33 3.4.1 PAM-4 DC BALANCE 35 3.4.2 PAM-4 TRANSITION DENSITY 35 3.4.3 10B6Q DECODER 37 3.5 IMPLEMENTATION AND MEASUREMENT RESULTS 40 CHAPTER 4 PAM-4 TRANSMITTER AND ADAPTIVE RECEIVER WITH FIXED DATA AND THRESHOLD LEVELS 45 4.1 INTRODUCTION 45 4.2 PRIOR WORKS 47 4.3 ARCHITECTURE AND IMPLEMENTATION 49 4.2.1 PAM-4 TRANSMITTER 49 4.2.2 PAM-4 ADAPTIVE RECEIVER 52 4.3 MEASUREMENT RESULTS 62 CHAPTER 5 ASYMMETRIC SIMULTANEOUS BIDIRECTIONAL TRANSCEIVERS USING WIDE LINEAR RANGE HYBRID 68 5.1 INTRODUCTION 68 5.2 PRIOR WORKS 70 5.3 WIDE LINEAR RANGE (WLR) HYBRID 75 5.3 IMPLEMENTATION 78 5.3.1 SERIALIZER (SER) DESIGN 78 5.3.2 DESERIALIZER (DES) DESIGN 79 5.4 HALF CIRCUIT ANALYSIS OF WLR HYBRID AND LRE 82 5.5 MEASUREMENT RESULTS 88 CHAPTER 6 CONCLUSION 97 BIBLIOGRAPHY 99 초 록 106박