A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications

In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for wideband applications. A common-gate input stage is used to improve the input impedance matching and linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure (NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply voltage of 0.8v

LNA for UWB transceiver using 0.18µm CMOS Technology

An Ultra WideBand CMOS Low Noise Amplifier (LNA) is presented. Due to really low power consumption and extremely high data rates the UWB standard is bound to be popular in the consumer market. The LNA is the outer most part of an UWB transceiver. The LNA is responsible for providing enough gain to the signal with the least distortion possible. CMOS 0.18µm TSMC technology has been chosen for the design of the LNA at the transistor level. As many as five on chip inductors are implemented for the proper gain shaping over the frequency range of 3.1GHz to 10.6GHz. A noise figure of 3.98 dB is achieved to make sure noise contribution of the amplifier is as low as possible

STRUCTURING AN LESS REGULATE RF FRONT-END CIRCUIT

Consequently, circuits operating from really low supply voltages have grown to be essential and therefore are underactive research. Our prime power consumption comes from the truth that an LNA must provide synchronized wideband matching, high gain, low noise, and linearity, which typically require high power and supply voltages. This paper presents a design methodology to have an ultra-low-power (ULP) and ultra-low-current (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed along with a new biasing metric for ULV and ULP designs in deep sub micrometer CMOS technologies is introduced. Exploiting the brand new biasing metric, the look methodology, and series inductive peaking within the feedback loop, a broadband LNA having a current reuse plan is implemented inside a CMOS technology. Series inductive peaking within the feedback loop is examined and used to boost the bandwidth and noise performance from the LNA

Design of a CMOS active electrode IC for wearable electrical impedance tomography systems

This paper describes the design of an active electrode integrated circuit (IC) for a wearable electrical impedance tomography (EIT) system required for real time monitoring of neonatal lung function. The IC comprises a wideband high power current driver (up to 6 mAp-p output current), a low noise voltage amplifier and two shape sensor buffers. The IC has been designed in a 0.35-μm CMOS technology. It operates from ±9 V power supplies and occupies a total die area of 5 mm2. Post-layout simulations are presented

Design of a CMOS active electrode IC for wearable electrical impedance tomography systems

This paper describes the design of an active electrode integrated circuit (IC) for a wearable electrical impedance tomography (EIT) system required for real time monitoring of neonatal lung function. The IC comprises a wideband high power current driver (up to 6 mAp-p output current), a low noise voltage amplifier and two shape sensor buffers. The IC has been designed in a 0.35-μm CMOS technology. It operates from ±9 V power supplies and occupies a total die area of 5 mm2. Post-layout simulations are presented

A Wideband Inductorless CMOS Front-End for Software Defined

The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. These standards heavily rely on digital signal processing, making CMOS the first technology of choice. However, RF CMOS circuit development is costly and time consuming due to mask costs and design iterations. This pleads for a Software Defined Radio approach, in which one piece of flexible radio hardware is re-used for different applications and standards, downloadable and under software control. To the best of our knowledge, little work has been done in this field based on CMOS technology. Recently, a bipolar downconverter front-end has been proposed [1]. In CMOS, only wideband low-noise amplifiers have been proposed, and some CMOS tuner ICs for satellite reception (which have less stringent noise requirements because they are preceded by an outdoor low-noise converter). This paper presents a wideband RF downconverter frontend in 0.18 um CMOS (also published in [2]), designed in the context of a research project exploring the feasibility of software defined radio, using a combined Bluetooth/WLAN receiver as a vehicle. Usually, RF receivers are optimised for low power consumption. In contrast, we have taken the approach to optimise for flexibility. The paper discusses the main system and circuit design choices, and assesses the achievable performance via measurements on a front-end implemented in 0.18um CMOS. The flexible design achieves a 0.2-2.2 GHz -3 dB bandwidth, a gain of 25 dB with 6 dB noise figure and +1 dBm IIP3

Wideband CMOS low noise amplifiers

Modern fully integrated receiver architectures, require inductorless circuits to achieve their potential low area, low cost, and low power. The low noise amplifier (LNA), which is a key block in such receivers, is investigated in this thesis. LNAs can be either narrowband or wideband. Narrowband LNAs use inductors and have very low noise figure, but they occupy a large area and require a technology with RF options to obtain inductors with high Q. Recently, wideband LNAs with noise and distortion cancelling, with passive loads have been proposed, which can have low NF, but have high power consumption. In this thesis the main goal is to obtain a very low area, low power, and low-cost wideband LNA. First, it is investigated a balun LNA with noise and distortion cancelling with active loads to boost the gain and reduce the noise figure (NF). The circuit is based on a conventional balun LNA with noise and distortion cancellation, using the combination of a common-gate (CG) stage and common-source (CS) stage. Simulation and measurements results, with a 130 nm CMOS technology, show that the gain is enhanced by about 3 dB and the NF is reduced by at least 0.5 dB, with a negligible impact on the circuit linearity (IIP3 is about 0 dBm). The total power dissipation is only 4.8 mW, and the active area is less than 50 x 50 m2 . It is also investigated a balun LNA in which the gain is boosted by using a double feedback structure.We propose to replace the load resistors by active loads, which can be used to implement local feedback loops (in the CG and CS stages). This will boost the gain and reduce the noise figure (NF). Simulation results, with the same 130 nm CMOS technology as above, show that the gain is 24 dB and NF is less than 2.7 dB. The total power dissipation is only 5.4 mW (since no extra blocks are required), leading to a figure-of-merit (FoM) of 3.8 mW1, using 1.2 V supply. The two LNA approaches proposed in this thesis are validated by simulation and by measurement results, and are included in a receiver front-end for biomedical applications (ISM and WMTS), as an example; however, they have a wider range of applications

A wideband high-linearity RF receiver front-end in CMOS

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 /spl mu/m CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise figure of 6.5 dB, +1 dBm IIP/sub 3/, +34.5 dBm IIP/sub 2/ and <50 kHz 1/f-noise corner frequency

A 1.2 V and 69 mW 60 GHz Multi-channel Tunable CMOS Receiver Design

A multi-channel receiver operating between 56 GHz and 70 GHz for coverage of different 60 GHz bands worldwide is implemented with a 90 nm Complementary Metal-Oxide Semiconductor (CMOS) process. The receiver containing an LNA, a frequency down-conversion mixer and a variable gain amplifier incorporating a band-pass filter is designed and implemented. This integrated receiver is tested at four channels of centre frequencies 58.3 GHz, 60.5 GHz, 62.6 GHz and 64.8 GHz, employing a frequency plan of an 8 GHz-intermediate frequency (IF). The achieved conversion gain by coarse gain control is between 4.8 dB–54.9 dB. The millimeter-wave receiver circuit is biased with a 1.2V supply voltage. The measured power consumption is 69 mW