4 research outputs found
Resource-Constrained Acquisition Circuits for Next Generation Neural Interfaces
The development of neural interfaces allowing the acquisition of signals from the cortex of the brain has seen an increasing amount of interest both in academic research as well as in the commercial space due to their ability to aid people with various medical conditions, such as spinal cord injuries, as well as their potential to allow more seamless interactions between people and machines. While it has already been demonstrated that neural implants can allow tetraplegic patients to control robotic arms, thus to an extent returning some motoric function, the current state of the art often involves the use of heavy table-top instruments connected by wires passing through the patient’s skull, thus making the applications impractical and chronically infeasible.
Those limitations are leading to the development of the next generation of neural interfaces that will overcome those issues by being minimal in size and completely wireless, thus paving a way to the possibility of their chronic application. Their development however faces several challenges in numerous aspects of engineering due to constraints presented by their minimal size, amount of power available as well as the materials that can be utilised.
The aim of this work is to explore some of those challenges and investigate novel circuit techniques that would allow the implementation of acquisition analogue front-ends under the presented constraints. This is facilitated by first giving an overview of the problematic of recording electrodes and their electrical characterisation in terms of their impedance profile and added noise that can be used to guide the design of analogue front-ends.
Continuous time (CT) acquisition is then investigated as a promising signal digitisation technique alternative to more conventional methods in terms of its suitability. This is complemented by a description of practical implementations of a CT analogue-to-digital converter (ADC) including a novel technique of clockless stochastic chopping aimed at the suppression of flicker noise that commonly affects the acquisition of low-frequency signals. A compact design is presented, implementing a 450 nW, 5.5 bit ENOB CT ADC, occupying an area of 0.0288 mm2 in a 0.18 μm CMOS technology, making this the smallest presented design in literature to the best of our knowledge.
As completely wireless neural implants rely on power delivered through wireless links, their supply voltage is often subject to large high frequency variations as well voltage uncertainty making it necessary to design reference circuits and voltage regulators providing stable reference voltage and supply in the constrained space afforded to them. This results in numerous challenges that are explored and a design of a practical implementation of a reference circuit and voltage regulator is presented. Two designs in a 0.35 μm CMOS technology are presented, showing respectively a measured PSRR of ≈60 dB and ≈53 dB at DC and a worst-case PSRR of ≈42 dB and ≈33 dB with a less than 1% standard deviation in the output reference voltage of 1.2 V while consuming a power of ≈7 μW.
Finally, ΣΔ modulators are investigated for their suitability in neural signal acquisition chains, their properties explained and a practical implementation of a ΣΔ DC-coupled neural acquisition circuit presented. This implements a 10-kHz, 40 dB SNDR ΣΔ analogue front-end implemented in a 0.18 μm CMOS technology occupying a compact area of 0.044 μm2 per channel while consuming 31.1 μW per channel.Open Acces
LOW POWER AND HIGH SIGNAL TO NOISE RATIO BIO-MEDICAL AFE DESIGN TECHNIQUES
The research work described in this thesis was focused on finding novel techniques to
implement a low-power and noise Bio-Medical Analog Front End (BMEF) circuit
technique to enable high-quality Electrocardiography (ECG) sensing. Usually, an ECG
signal and several bio-medical signals are sensed from the human body through a pair
of electrodes. The electrical characteristics of the very small amplitude (1u-10mV)
signals are corrupted by random noise and have a significant dc offset. 50/60Hz power
supply coupling noise is one of the biggest cross-talk signals compared to the thermally
generated random noise. These signals are even AFE composed of an Instrumentation
Amplifier (IA), which will have a better Common Mode rejection ratio (CMRR). The main
function of the AFE is to convert the weak electrical Signal into large signals whose
amplitude is large enough for an Analog Digital Converter (ADC) to detect without having
any errors. A Variable Gain Amplifier (VGA) is sometimes required to adjust signal
amplitude to maintain the dynamic range of the ADC. Also, the Bio-medical transceiver
needs an accurate and temperature-independent reference voltage and current for the
ADC, commonly known as Bandgap Reference Circuit (BGR). These circuits need to
consume as low power as possible to enable these circuits to be powered from the
battery.
The work started with analysing the existing circuit techniques for the circuits
mentioned above and finding the key important improvements required to reach the
target specifications. Previously proposed IA is generated based on voltage mode signal
processing. To improve the CMRR (119dB), we proposed a current mode-based IA with
an embedded DC cancellation technique. State-of-the-art VGA circuits were built based
on the degeneration principle of the differential pair, which will enable the variable gain
purpose, but none of these techniques discussed linearity improvement, which is very
important in modern CMOS technologies. This work enhances the total Harmonic
distortion (THD) by 21dB in the worst case by exploiting the feedback techniques around
the differential pair. Also, this work proposes a low power curvature compensated
bandgap with 2ppm/0C temperature sensitivity while consuming 12.5uW power from a
1.2V dc power supply. All circuits were built in 45nm TSMC-CMOS technology and
simulated with all the performance metrics with Cadence (spectre) simulator. The circuit
layout was carried out to study post-layout parasitic effect sensitivity