HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

Design of low power CMOS UWB transceiver ICs

Master'sMASTER OF ENGINEERIN

Design of Cognitive Radios

Cognitive radios are expected to perform spectrum sensing and communication in the frequency range of tens of megahertz to about 10 GHz. As such, they pose tough architecture and circuit design problems. This paper deals with issues such as broadband, low-noise amplification, multidecade carrier frequency synthesis, and spectrum sensing. The paper also describes the effect of nonlinearity and local oscillator harmonics, demonstrating that cognitive radios entail more difficult challenges than do software-defined radios. Multi-decade synthesis techniques and RF-assisted sensing methods are also presented

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

High Performance LNAs and Mixers for Direct Conversion Receivers in BiCMOS and CMOS Technologies

The trend in cellular chipset design today is to incorporate support for a larger number of frequency bands for each new chipset generation. If the chipset also supports receiver diversity two low noise amplifiers (LNAs) are required for each frequency band. This is however associated with an increase of off-chip components, i.e. matching components for the LNA inputs, as well as complex routing of the RF input signals. If balanced LNAs are implemented the routing complexity is further increased. The first presented work in this thesis is a novel multiband low noise single ended LNA and mixer architecture. The mixer has a novel feedback loop suppressing both second order distortion as well as DC-offset. The performance, verified by Monte Carlo simulations, is sufficient for a WCDMA application. The second presented work is a single ended multiband LNA with programmable integrated matching. The LNA is connected to an on-chip tunable balun generating differential RF signals for a differential mixer. The combination of the narrow band input matching and narrow band balun of the presented LNA is beneficial for suppressing third harmonic downconversion of a WLAN interferer. The single ended architecture has great advantages regarding PCB routing of the RF input signals but is on the other hand more sensitive to common mode interferers, e.g. ground, supply and substrate noise. An analysis of direct conversion receiver requirements is presented together with an overview of different LNA and mixer architectures in both BiCMOS and CMOS technology

Blocker Tolerant Radio Architectures

Future radio platforms have to be inexpensive and deal with a variety of co- existence issues. The technology trend during the last few years is towards system- on-chip (SoC) that is able to process multiple standards re-using most of the digital resources. A major bottle-neck to this approach is the co-existence of these standards operating at different frequency bands that are hitting the receiver front-end. So the current research is focused on the power, area and performance optimization of various circuit building blocks of a radio for current and incoming standards. Firstly, a linearization technique for low noise amplifiers (LNAs) called, Robust Derivative Superposition (RDS) method is proposed. RDS technique is insensitive to Process Voltage and Temperature (P.V.T.) variations and is validated with two low noise transconductance amplifier (LNTA) designs in 0.18µm CMOS technology. Measurement results from 5 dies of a resistive terminated LNTA shows that the pro- posed method improves IM3 over 20dB for input power up to -18dBm, and improves IIP_(3) by 10dB. A 2V inductor-less broadband 0.3 to 2.8GHz balun-LNTA employing the proposed RDS linearization technique was designed and measured. It achieves noise figure of 6.5dB, IIP3 of 16.8dBm, and P1dB of 0.5dBm having a power consumption of 14.2mW. The balun LNTA occupies an active area of 0.06mm2. Secondly, the design of two high linearity, inductor-less, broadband LNTAs employing noise and distortion cancellation techniques is presented. Main design issues and the performance trade-offs of the circuits are discussed. In the fully differential architecture, the first LNTA covers 0.1-2GHz bandwidth and achieves a minimum noise figure (NFmin) of 3dB, IIP_(3) of 10dBm and a P_(1dB) of 0dBm while dissipating 30.2mW. The 2^(nd) low power bulk driven LNTA with 16mW power consumption achieves NFmin of 3.4dB, IIP3 of 11dBm and 0.1-3GHz bandwidth. Each LNTA occupy an active area of 0.06mm2 in 45nm CMOS. Thirdly, a continuous-time low-pass ∆ΣADC equipped with design techniques to provide robustness against loop saturation due to blockers is presented. Loop over- load detection and correction is employed to improve the ADC’s tolerance to blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADC’s blocker tolerance, a minimally-invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. An ADC prototype is implemented in a 90nm CMOS technology and experimentally it achieves 69dB dynamic range over a 20MHz bandwidth with a sampling frequency of 500MHz and 17.1mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5dBFS while the conventional feed-forward modulator becomes unstable at -23.5dBFS of blocker power. The proposed blocker rejection techniques are minimally-invasive and take less than 0.3µsec to settle after a strong agile blocker appears. Finally, a new radio partitioning methodology that gives robust analog and mixed signal radio development in scaled technology for SoC integration, and the co-design of RF FEM-antenna system is presented. Based on the proposed methodology, a CMOS RF front-end module (FEM) with power amplifier (PA), LNA and transmit/receive switch, co-designed with antenna is implemented. The RF FEM circuit is implemented in a 32nm CMOS technology. Post extracted simulations show a noise figure < 2.5dB, S_(21) of 14dB, IIP3 of 7dBm and P1dB of -8dBm for the receiver. Total power consumption of the receiver is 11.8mW from a 1V supply. On the trans- mitter side, PA achieves peak RF output power of 22.34dBm with peak power added efficiency (PAE) of 65% and PAE of 33% with linearization at -6dB power back off. Simulations show an efficiency of 80% for the miniaturized dipole antenna

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

Parametric analog signal amplification applied to nanoscale cmos wireless digital transceivers

Thesis presented in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the subject of Electrical and Computer Engineering by the Universidade Nova de Lisboa,Faculdade de Ciências e TecnologiaSignal amplification is required in almost every analog electronic system. However noise is also present, thus imposing limits to the overall circuit performance, e.g., on the sensitivity of the radio transceiver. This drawback has triggered a major research on the field, which has been producing several solutions to achieve amplification with minimum added noise. During the Fifties, an interesting out of mainstream path was followed which was based on variable reactance instead of resistance based amplifiers. The principle of these parametric circuits permits to achieve low noise amplifiers since the controlled variations of pure reactance elements is intrinsically noiseless. The amplification is based on a mixing effect which enables energy transfer from an AC pump source to other related signal frequencies. While the first implementations of these type of amplifiers were already available at that time, the discrete-time version only became visible more recently. This discrete-time version is a promising technique since it is well adapted to the mainstream nanoscale CMOS technology. The technique itself is based on the principle of changing the surface potential of the MOS device while maintaining the transistor gate in a floating state. In order words, the voltage amplification is achieved by changing the capacitance value while maintaining the total charge unchanged during an amplification phase. Since a parametric amplifier is not intrinsically dependent on the transconductance of the MOS transistor, it does not directly suffer from the intrinsic transconductance MOS gain issues verified in nanoscale MOS technologies. As a consequence, open-loop and opamp free structures can further emerge with this additional contribution. This thesis is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. The use of the latter is supported on the presentation of several circuits where the MOS Parametric Amplifier cell is well suited: small gain amplifier, comparator, discrete-time mixer and filter, and ADC. Relatively to the latter, a high speed time-interleaved pipeline ADC prototype is implemented in a,standard 130 nm CMOS digital technology from United Microelectronics Corporation (UMC). The ADC is fully based on parametric MOS amplification which means that one could achieve a compact and MOS-only implementation. Furthermore, any high speed opamp has not been used in the signal path, being all the amplification steps implemented with open-loop parametric MOS amplifiers. To the author’s knowledge, this is first reported pipeline ADC that extensively used the parametric amplification concept.Fundação para a Ciência e Tecnologia through the projects SPEED, LEADER and IMPAC

Low-Power Integrated Circuits For Biomedical Applications

With thousands new cases of spinal cord injury reported everyday, many people suffer from paralysis and loss of sensation in both legs. Beside the healthcare costs, such a state severely deteriorates the patients' quality of life and may even lead to additional medical conditions. Therefore, there is a growing need for cyber-physical systems to restore the walking ability through bypassing the damaged spinal cord. This goal can be achieved by monitoring and processing patient's brain signals to enable brain-directed control of prosthetic legs. Among several existing methods to record brain signals, electrocorticography (ECoG) has gained popularity due to being robust to motion artifacts, having high spatial resolution and signal to noise ratio, being moderately invasive and the possibility of chronic implantation of recording grids with no or minor scar tissue formation. The latest property is of particular importance for the whole system to be a viable fully implantable solution. Furthermore, the implanted system has to operate independently with no or minimal need of external hardware (e.g. a bulky personal computer) to be individually and socially accepted. To implement a fully implantable system, low-power and miniaturized electronics are needed to reduced heat generation, increase battery life-time and be minimally intrusive. These requirements indicate that many of the system's components should be custom-designed to integrated as much functionality as possible in a given real estate. This thesis presents silicon tested prototypes of several building blocks for the envisioned system, namely, ultra low-power brain signal acquisition front-ends, a low-power and inductorless MedRadio transceiver, and a fast start-up crystal oscillator. Brain signal acquisition front-ends provide low noise amplification of weak ECoG biosignals. MedRadio transceiver enables communication between the implant and end effectors or base station (e.g. prosthetic legs or desktop computer). Crystal oscillator generates the reference signal for other system's components such as analog to digital converter. Novel techniques to improve important performance parameters (power consumption, low noise operation and interference resilience) have been introduced. Electrical, in-vitro and in-vivo experimental measurements have verified the functionality and performance of each design

Design of CMOS transimpedance amplifiers for remote antenna units in fiber-wireless systems.

La memoria de la tesis doctoral: Diseño de Amplificadores de Transimpedancia para Unidades de Antena Remota en Sistemas Fibra-Inalámbrico, se presenta en la modalidad de compendio de Publicaciones. A continuación, se expone un resumen del contexto, motivation y objetivos de la tesis.A lo largo de las últimas décadas, los avances tecnológicos y el esfuerzo por desarrollar nuevos sistemas de comunicaciones han crecido al ritmo que la demanda de información aumentaba a nivel mundial. Desde la aparición de Internet, el tráfico global de datos ha incrementado de forma exponencial y se han creado infinidad de aplicaciones y contenidos desde entonces.Con la llegada de la fibra óptica se produjo un avance muy significativo en el campo de las comunicaciones, ya que la fibra de vidrio y sus características fueron la clave para crear redes de largo alcance y alta velocidad. Por otro lado, los avances en las tecnologías de fabricación de circuitos integrados y de dispositivos fotónicos de alta velocidad han encabezado el desarrollo de los sistemas de comunicaciones ópticos, logrando incrementar la tasa de transmisión de datos hasta prácticamente alcanzar el ancho de banda de la fibra óptica.Para conseguir una mayor eficiencia en las comunicaciones y aumentar la tasa de transferencia, se necesitan métodos de modulación complejos que aprovechen mejor el ancho de banda disponible. No obstante, esta mayor complejidad de la modulación de los datos requiere sistemas con mejores prestaciones en cuanto a rango dinámico y linealidad. Estos esquemas de modulación se emplean desde hace tiempo en los sistemas de comunicaciones inalámbricos, donde el ancho de banda del canal, el aire, es extremadamente limitado y codiciado.Actualmente, los sistemas inalámbricos se enfrentan a una saturación del espectro que supone un límite a la tasa de transmisión de datos. Pese a los esfuerzos por extender el rango frecuencial a bandas superiores para aumentar el ancho de banda disponible, se espera un enorme aumento tanto en el número de dispositivos, como en la cantidad de datos demandados por usuario.Ante esta situación se han planteado distintas soluciones para superar estas limitaciones y mejorar las prestaciones de los sistemas actuales. Entre estas alternativas están los sistemas mixtos fibra-inalámbrico utilizando sistemas de antenas distribuidas (DAS). Estos sistemas prometen ser una solución económica y muy efectiva para mejorar la accesibilidad de los dispositivos inalámbricos, aumentando la cobertura y la tasa de transferencia de las redes a la vez que disminuyen las interferencias. El despliegue de los DAS tendrá un gran efecto en escenarios tales como edificios densamente poblados, hospitales, aeropuertos o edificios de oficinas, así como en áreas residenciales, donde un gran número de dispositivos requieren una cada vez mayor interconectividad.Dependiendo del modo de transmisión de los datos a través de la fibra, los sistemas mixtos fibra-inalámbrico se pueden categorizar de tres formas distintas: Banda base sobre fibra (BBoF), radiofrecuencia sobre fibra (RFoF) y frecuencia intermedia sobre fibra (IFoF). Actualmente, el esquema BBoF es el más utilizado para transmisiones de larga y media distancia. No obstante, utilizar este esquema en un DAS requiere unidades de antena remota (RAU) complejas y costosas, por lo que no está claro que esta configuración pueda ser viable en aplicaciones de bajo coste que requieran de un gran número de RAUs. Los sistemas RFoF e IFoF presentan esquemas más simples, sin necesidad de integrar un modulador/demodulador, puesto que la señal se procesa en una estación base y no en las propias RAUs.El desarrollo de esta tesis se enmarca en el estudio de los distintos esquemas de DAS. A lo largo de esta tesis se presentan varias propuestas de amplificadores de transimpedancia (TIA) adecuadas para su implementación en cada uno de los tres tipos de RAU existentes. La versatilidad y el amplio campo de aplicación de este circuito integrado, tanto en comunicaciones como en otros ámbitos, han motivado el estudio de la implementación de este bloque específico en las diferentes arquitecturas de RAU y en otros sistemas, tales como un receptor de televisión por cable (CATV) o una interfaz de un microsensor inercial capacitivo.La memoria de tesis se ha dividido en tres capítulos. El Capítulo 1 se ha empleado para introducir el concepto de los DAS, proporcionando el contexto y la motivación del diseño de las RAU, partiendo desde los principios básicos de operación de los dispositivos fotónicos y electrónicos y presentando las distintas arquitecturas de RAU. El Capítulo 2 supone el núcleo principal de la tesis. En este capítulo se presenta el estudio y diseño de los diferentes TIAs, que han sido optimizados respectivamente para cada una de las configuraciones de RAU, así como para otras aplicaciones. En un tercer capítulo se recogen los resultados más relevantes y se exponen las conclusiones de este trabajo.Tras llevar a cabo la descripción y comparación de las topologías existentes de TIA, se ha llegado a las siguientes conclusiones, las cuales nos llevan a elegir la topología shunt-feedback como la más adecuada para el diseño: - El compromiso entre ancho de banda, transimpedancia, consumo de potencia y ruido es menos restrictivo en los TIAs de lazo cerrado. - Los TIAs de lazo cerrado tienen un mayor número de grados de libertad para acometer su diseño. - Esta topología presenta una mejor linealidad gracias al lazo de realimentación. Si la respuesta frecuencial del núcleo del amplificador se ajusta de manera adecuada, el TIA shunt-feedback puede presentar una respuesta frecuencial plana y estable.En esta tesis, se ha propuesto una nueva técnica de reducción de ruido, aplicable en receptores ópticos con fotodiodos con un área activa grande (~1mm2). Esta estrategia, que se ha llamado la técnica del fotodiodo troceado, consiste en la fabricación del fotodiodo, no como una estructura única, sino como un array de N sub-fotodiodos, que ocuparían la misma área activa que el original. Las principales conclusiones tras hacer un estudio teórico y realizar un estudio de su aplicación en una de las topologías de TIA propuestas son: - El ruido equivalente a la entrada es menor cuanto mayor es el número de sub-fotodiodos, dado que la contribución al ruido que depende con el cuadrado de la frecuencia (f^2) decrece con una dependencia proporcional a N. - Con una aplicación simple de la técnica, replicando el amplificador de tensión del TIA N veces y utilizando N resistencias de realimentación, cada una con un valor N veces el original, la sensibilidad del receptor aumenta aproximadamente en un factor √N y la estabilidad del sistema no se ve afectada. - Al dividir el fotodiodo en N sub-fotodiodos, la capacidad parásita de cada uno de ellos es N veces menor a la original. Con esta nueva capacidad parásita, el diseño del TIA se puede optimizar, consiguiendo una sensibilidad mucho mejor que con un único fotodiodo para el mismo valor de consumo de potencia.Las principales conclusiones respecto a los diseños de los distintos TIAs para comunicaciones son las siguientes: TIA para BBoF: - El TIA propuesto, alcanza, con un consumo de tan solo 2.9 mW, un ancho de banda de 1 GHz y una sensibilidad de -11 dBm, superando las características de trabajos anteriores en condiciones similares (capacidad del fotodiodo, tecnología y tasa de transmisión). - La técnica del fotodiodo troceado se ha aplicado a este circuito, consiguiendo una mejora de hasta 7.9 dBm en la sensibilidad para un diseño optimizado de 16 sub-fotodiodos, demostrando, en una simulación a nivel de transistor, que la técnica propuesta funciona correctamente. TIA para RFoF: - El diseño propuesto logra una figura de mérito superior a la de trabajos previos, gracias a la combinación de su bajo consumo de potencia y su mayor transimpedancia. - Además, mientras que en la mayoría de trabajos previos no se integra un control de ganancia en el TIA, esta propuesta presenta una transimpedancia controlable desde 45 hasta 65 dBΩ. A través de un sistema de control simultáneo de la transimpedancia y de la ganancia en lazo abierto del amplificador de voltaje, se consigue garantizar una respuesta frecuencial plana y estable en todos los estados de transimpedancia, que le otorga al diseño una superior versatilidad y flexibilidad. TIA para CATV: - Se ha adaptado una versión del TIA para RFoF para demostrar la capacidad de adaptación de esta estructura en una implementación en un receptor CATV con un rango de control de transimpedancia de 18 dB. - Con la implementación del control de ganancia en el TIA, no es necesario el uso de un atenuador variable en el receptor, simplificando así el número de etapas del mismo. - Gracias al control de transimpedancia, el TIA logra rangos de entrada similares a los publicados en trabajos anteriores basados en una tecnología mucho menos accesible como GaAs PHEMT. TIA para IFoF Se ha fabricado un chip en una tecnología CMOS de 65 nm que opera a 1.2 V de tensión de alimentación y se ha realizado su caracterización eléctrica y óptica. - El TIA presenta una programabilidad de su transimpedancia con un control lineal en dB entre 60 y 76 dBΩ mediante un código termómetro de 4 bits. - El ancho de banda se mantiene casi constante en todo el rango de transimpedancia, entre 500 y 600 MHz.Como conclusión general tras comparar el funcionamiento de los TIAs para las distintas configuraciones de RAU, vale la pena mencionar que el TIA para IFoF consigue una figura de mérito muy superior a la de otros trabajos previos diseñados para RFoF. Esto se debe principalmente a la mayor transimpedancia y al muy bajo consumo de potencia del TIA para IFoF propuesto. Además, se consigue una mejor linealidad, ya que, para una transmisión de 54 Mb/s con el estándar 802.11a, se consigue un EVM menor de 2 % en un rango de entrada de 10 dB, comparado con los entre 3 y 5 dB reportados en trabajos previos. El esquema IFoF presenta un gran potencial y ventajas frente al RFoF, lo que lo coloca como una buena alternativa para disminuir los costes y mejorar el rendimiento de los sistemas de antenas distribuidas.Por último, cabe destacar que el diseño de TIA propuesto y fabricado para IFoF contribuye en gran medida al desarrollo y validación de una RAU completa. Se ha demostrado la capacidad de la estructura propuesta para alcanzar un bajo ruido, alta linealidad, simplicidad en la programabilidad de la transimpedancia y adaptabilidad de la topología para diferentes requisitos, lo cual es de un gran interés en el diseño de receptores ópticos.Por otra parte, una versión del TIA para su uso en una interfaz de sensores MEMS capacitivos se ha propuesto y estudiado. Consiste en un convertidor capacidad-voltaje basado en una versión del TIA para RFoF, con el objetivo de conseguir un menor ruido y proveer de una adaptabilidad para diferentes sensores capacitivos. Los resultados más significativos y las conclusiones de este diseño se resumen a continuación: - El TIA presenta un control de transimpedancia con un rango de 34 dB manteniendo el ancho de banda constante en 1.2 MHz. También presenta un control independiente del ancho de banda, desde 75 kHz hasta 1.2 MHz, manteniendo la transimpedancia fija en un valor máximo. - Con un consumo de potencia de tan solo 54 μW, el TIA alcanza una sensibilidad máxima de 1 mV/fF, que corresponde a una sensibilidad de 4.2 mV/g y presenta un ruido de entrada de tan solo 100 µg/√("Hz" ) a 50 kHz en la configuración de máxima transimpedancia.La principal conclusión que destaca de este diseño es su versatilidad y flexibilidad. El diseño propuesto permite adaptar fácilmente la respuesta de la interfaz a una amplia gama de dispositivos sensores, ya que se puede ajustar el ancho de banda para ajustarse a distintas frecuencias de operación, así como la transimpedancia puede ser modificada para conseguir distintas sensibilidades. Este doble control independiente de ancho de banda y transimpedancia le proporcionan una adaptabilidad completa al TIA.<br /