Sequential Challenges in Synthesizing Esterel

State assignment is a formidable task. As designs written in a hardware description language such as Esterel inherently carry more high level information that a register transfer level model, such information can be used to guide the encoding process. A question arises if the high level information alone is strong enough to suggest an efficient state assignment, allowing low-level details to be ignored. This report suggests that with Esterel's flexibility, most optimization potential is not within the high-level structure. It appears effective state assignment cannot rely solely on high level information

Sequential Challenges in Synthesizing Esterel

State assignment is a formidable task. As designs written in a hardware description language such as Esterel inherently carry more high level information that a register transfer level model, such information can be used to guide the encoding process. A question arises if the high level information alone is strong enough to suggest an efficient state assignment, allowing low-level details to be ignored. This report suggests that with Esterel's flexibility, most optimization potential is not within the high-level structure. It appears effective state assignment cannot rely solely on high level information

Approximate Reachability for Dead Code Elimination in Esterel*

Esterel is an imperative synchronous programming language for the design of reactive systems. Esterel* extends Esterel with a non-instantaneous jump instruction (compatible with concurrency, preemption, etc.) so as to enable powerful source-to-source program transformations, amenable to formal verification. In this work, we propose an approximate reachability algorithm for Esterel* and use its output to remove dead code. We prove the correctness of our techniques

Verifying hardware compilers

The use of hardware compilers to generate complex circuits from a high-level description is becoming more and more prevalent in a variety of application areas. However, this introduces further risks as the compilation process may introduce errors in otherwise correct high-level descriptions of circuits. In this paper, we present techniques to enable the automatic verification of hardware compilers through the use of finite-state model checkers. We illustrate the use of these techniques on a simple regular expression hardware compiler and discuss how these techniques can be further developed and used on more complex hardware- description languages.peer-reviewe

The GENCOD project : Automated generation of Hardware code for safety critical applications on FPGA targets

International audienceGENCOD is a research project for solutions to automated generation of safe code for Field Programmable Gate Arrays (FPGA) targets. The paper will describe typical ASIC/FPGA workflow, and current implementation for airborne electronic hardware design. Major stakes in certification for airborne electronic hardware will be discussed. The next part will detail the project, the proposed workflow and the associated tools. We will present the current experimentations. Finally, the conclusion will expose advantages and drawbacks of such approach