3,689 research outputs found
Floyd-Warshall Algorithm 1
Abstract: There are several applications in VLSI technology that require high-speed shortest-path computations. The shortest path is a path between two nodes (or points) in a graph such that the sum of the weights of its constituent edges is minimum. Floyd-Warshall algorithm provides fastest computation of shortest path between all pair of nodes present in the graph. With rapid advances in VLSI technology, Field Programmable Gate Arrays (FPGAs) are receiving the attention of the Parallel and High Performance Computing community. This paper gives implementation outcome of Floyd-Warshall algorithm to solve the all pairs shortest-paths problem for directed graph in Verilog
Routing for analog chip designs at NXP Semiconductors
During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP.
This resulted in an heuristic approach, which we presented at the end of the
week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach
A VLSI DSP DESIGN AND IMPLEMENTATION OF ALL POLE LATTICE FILTER USING RETIMING METHODOLOGY
All pole lattice fil ters are used in a variety of signal processing applications that is speech processing, adaptive filters and various other applications. The implementation of lattice f i l t e r requires more clock period hence low speed. There are various transformation technique pr es ent for design of high-speed or low-area or lowpower implementations. This paper presents design of high-speed (smaller clock period) implementation of 8th order all pole lattice filter using the methodology named as Retiming. Retiming reduces the clock period of the circuit, reducing the number of registers in the circuit, reducing the power consumption of the circuit. Therefore, retiming has been used to reduce the clock period of all pole lattice filters and it increases the speed of the system
The edge-disjoint path problem on random graphs by message-passing
We present a message-passing algorithm to solve the edge disjoint path
problem (EDP) on graphs incorporating under a unique framework both traffic
optimization and path length minimization. The min-sum equations for this
problem present an exponential computational cost in the number of paths. To
overcome this obstacle we propose an efficient implementation by mapping the
equations onto a weighted combinatorial matching problem over an auxiliary
graph. We perform extensive numerical simulations on random graphs of various
types to test the performance both in terms of path length minimization and
maximization of the number of accommodated paths. In addition, we test the
performance on benchmark instances on various graphs by comparison with
state-of-the-art algorithms and results found in the literature. Our
message-passing algorithm always outperforms the others in terms of the number
of accommodated paths when considering non trivial instances (otherwise it
gives the same trivial results). Remarkably, the largest improvement in
performance with respect to the other methods employed is found in the case of
benchmarks with meshes, where the validity hypothesis behind message-passing is
expected to worsen. In these cases, even though the exact message-passing
equations do not converge, by introducing a reinforcement parameter to force
convergence towards a sub optimal solution, we were able to always outperform
the other algorithms with a peak of 27% performance improvement in terms of
accommodated paths. On random graphs, we numerically observe two separated
regimes: one in which all paths can be accommodated and one in which this is
not possible. We also investigate the behaviour of both the number of paths to
be accommodated and their minimum total length.Comment: 14 pages, 8 figure
Recent Advances in Graph Partitioning
We survey recent trends in practical algorithms for balanced graph
partitioning together with applications and future research directions
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures
Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network- on-Chip (NoC) paradigm is an interesting option to achieve flexibility, but several design choices, including the topology and the routing algorithm, can affect the decoder throughput. In this work logarithmic diameter topologies, in particular generalized de-Bruijn and Kautz topologies, are addressed as possible solutions to achieve both flexible and high throughput architectures for iterative channel code decoding. In particular, this work shows that the optimal shortest-path routing algorithm for these topologies, that is still available in the open literature, can be efficiently implemented resorting to a very simple circuit. Experimental results show that the proposed architecture features a reduction of about 14% and 10% for area and power consumption respectively, with respect to a previous shortest-path routing-table-based desig
Edge Routing with Ordered Bundles
Edge bundling reduces the visual clutter in a drawing of a graph by uniting
the edges into bundles. We propose a method of edge bundling drawing each edge
of a bundle separately as in metro-maps and call our method ordered bundles. To
produce aesthetically looking edge routes it minimizes a cost function on the
edges. The cost function depends on the ink, required to draw the edges, the
edge lengths, widths and separations. The cost also penalizes for too many
edges passing through narrow channels by using the constrained Delaunay
triangulation. The method avoids unnecessary edge-node and edge-edge crossings.
To draw edges with the minimal number of crossings and separately within the
same bundle we develop an efficient algorithm solving a variant of the
metro-line crossing minimization problem. In general, the method creates clear
and smooth edge routes giving an overview of the global graph structure, while
still drawing each edge separately and thus enabling local analysis
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