Computer tools for systems engineering at LaRC

The Systems Engineering Office (SEO) has been established to provide life cycle systems engineering support to Langley research Center projects. over the last two years, the computing market has been reviewed for tools which could enhance the effectiveness and efficiency of activities directed towards this mission. A group of interrelated applications have been procured, or are under development including a requirements management tool, a system design and simulation tool, and project and engineering data base. This paper will review the current configuration of these tools and provide information on future milestones and directions

A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile

International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building com- plex systems remains a daunting task. Recently, approaches based on Model-Driven Engi- neering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to ex- ecutable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration

Особенности проектирования компьютерных систем на кристалле ПЛИС

На основании анализа отечественных и зарубежных публикаций определены особенности проектирования «системы на кристалле» ПЛИС (System on Chip-SoC), включающей сложные функциональные блоки (СФ-блоки), а также встроенные процессорные ядра. При этом представлены возможные типы СФ-блоков, а также программного обеспечения, и определены проблемы, возникающие при проектировании. Приведены параметры некоторых синтезируемых СФ-блоков, а также информация о маршруте проектирования проекта на кристалле.На підставі аналізу вітчизняних і закордонних публікацій визначені особливості проектування «системи на кристалі» ПЛІС (System on Chіp-SoС), що включає складні функціональні блоки (СФ-блоки), а також вбудовані процесорні ядра. При цьому представлені можливі типи СФ-блоків, а також програмного забезпечення, та визначені проблеми, що виникають при проектуванні. Наведено параметри деяких синтезованих СФ-блоків, а також інформацію про маршрут проектування проекту на кристалі.On the bases of the analysis of domestic and foreign publications there were defined the features of designing “systems on a crystal” FPGA (System on Chip-SoC), including difficult functional blocks (DFblocks) as well as the built in processor cores. Moreover there were presented the possible types of DFblocks and software arising at designing. The parametres of some synthesized processor DF-blocks as well as brief information about results of two developed projects on a crystal are resulted

An Adaptive Design Methodology for Reduction of Product Development Risk

Embedded systems interaction with environment inherently complicates understanding of requirements and their correct implementation. However, product uncertainty is highest during early stages of development. Design verification is an essential step in the development of any system, especially for Embedded System. This paper introduces a novel adaptive design methodology, which incorporates step-wise prototyping and verification. With each adaptive step product-realization level is enhanced while decreasing the level of product uncertainty, thereby reducing the overall costs. The back-bone of this frame-work is the development of Domain Specific Operational (DOP) Model and the associated Verification Instrumentation for Test and Evaluation, developed based on the DOP model. Together they generate functionally valid test-sequence for carrying out prototype evaluation. With the help of a case study 'Multimode Detection Subsystem' the application of this method is sketched. The design methodologies can be compared by defining and computing a generic performance criterion like Average design-cycle Risk. For the case study, by computing Average design-cycle Risk, it is shown that the adaptive method reduces the product development risk for a small increase in the total design cycle time.Comment: 21 pages, 9 figure

Towards a Scalable Hardware/Software Co-Design Platform for Real-time Pedestrian Tracking Based on a ZYNQ-7000 Device

Currently, most designers face a daunting task to research different design flows and learn the intricacies of specific software from various manufacturers in hardware/software co-design. An urgent need of creating a scalable hardware/software co-design platform has become a key strategic element for developing hardware/software integrated systems. In this paper, we propose a new design flow for building a scalable co-design platform on FPGA-based system-on-chip. We employ an integrated approach to implement a histogram oriented gradients (HOG) and a support vector machine (SVM) classification on a programmable device for pedestrian tracking. Not only was hardware resource analysis reported, but the precision and success rates of pedestrian tracking on nine open access image data sets are also analysed. Finally, our proposed design flow can be used for any real-time image processingrelated products on programmable ZYNQ-based embedded systems, which benefits from a reduced design time and provide a scalable solution for embedded image processing products

The hArtes Tool Chain

This chapter describes the different design steps needed to go from legacy code to a transformed application that can be efficiently mapped on the hArtes platform

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study

International audienceIn this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MARTE that abstracts the technologic aspects of the chosen back-end. The so- obtained UML platform is transformed in an IP-XACT design, which is exploited to generate the files used by XPS for system implementation. In this way, we promote IP reuse and deployment while remaining back-end independent, by using specific vendor extensions. Finally, we analyze the advantages of the proposed methodology by a case study in system integration

Congruent Weak Conformance

This research addresses the problem of verifying implementations against specifications through an innovative logic approach. Congruent weak conformance, a formal relationship between agents and specifications, has been developed and proven to be a congruent partial order. This property arises from a set of relations called weak conformations. The largest, called weak conformance, is analogous to Milner\u27s observational equivalence. Weak conformance is not an equivalence, however, but rather an ordering relation among processes. Weak conformance allows behaviors in the implementation that are unreachable in the specification. Furthermore, it exploits output concurrencies and allows interleaving of extraneous output actions in the implementation. Finally, reasonable restrictions in CCS syntax strengthen weak conformance to a congruence, called congruent weak conformance. At present, congruent weak conformance is the best known formal relation for verifying implementations against specifications. This precongruence derives maximal flexibility and embodies all weaknesses in input, output, and no-connect signals while retaining a fully replaceable conformance to the specification. Congruent weak conformance has additional utility in verifying transformations between systems of incompatible semantics. This dissertation describes a hypothetical translator from the informal simulation semantics of VHDL to the bisimulation semantics of CCS. A second translator is described from VHDL to a broadcast-communication version of CCS. By showing that they preserve congruent weak conformance, both translators are verified

Rapid prototyping modules for remote engineering applications

This contribution describes a concept for an integration of microcontroller- and FPGA-based Rapid Prototyping modules into a Remote Lab system and its implementation. The implementation enables a Web-based access to control electro-mechanical models. The electromechanical models can be controlled by different platforms (microcontroller or FPGA-based) Students have the possibility to test a designed control algorithm directly within a hardware environment by uploading a source file to the Remote Lab server. That way the students can compare architectures of different control-platforms as well as different design approaches to control electro-mechanical models. The paper starts with an introduction into the design process and describes the tool set, which is provided to the students. After that the different platforms and their integration in the Web-server are introduced. Finally we would like to give examples of such complex design tasks and show, how the students can use different tools during several design steps