High-Bandwidth Voltage-Controlled Oscillator based architectures for Analog-to-Digital Conversion

The purpose of this thesis is the proposal and implementation of data conversion open-loop architectures based on voltage-controlled oscillators (VCOs) built with ring oscillators (RO-based ADCs), suitable for highly digital designs, scalable to the newest complementary metal-oxide-semiconductor (CMOS) nodes. The scaling of the design technologies into the nanometer range imposes the reduction of the supply voltage towards small and power-efficient architectures, leading to lower voltage overhead of the transistors. Additionally, phenomena like a lower intrinsic gain, inherent noise, and parasitic effects (mismatch between devices and PVT variations) make the design of classic structures for ADCs more challenging. In recent years, time-encoded A/D conversion has gained relevant popularity due to the possibility of being implemented with mostly digital structures. Within this trend, VCOs designed with ring oscillator based topologies have emerged as promising candidates for the conception of new digitization techniques. RO-based data converters show excellent scalability and sensitivity, apart from some other desirable properties, such as inherent quantization noise shaping and implicit anti-aliasing filtering. However, their nonlinearity and the limited time delay achievable in a simple NOT gate drastically limits the resolution of the converter, especially if we focus on wide-band A/D conversion. This thesis proposes new ways to alleviate these issues. Firstly, circuit-based techniques to compensate for the nonlinearity of the ring oscillator are proposed and compared to equivalent state-of-the-art solutions. The proposals are designed and simulated in a 65-nm CMOS node for open-loop RO-based ADC architectures. One of the techniques is also validated experimentally through a prototype. Secondly, new ways to artificially increase the effective oscillation frequency are introduced and validated by simulations. Finally, new approaches to shape the quantization noise and filter the output spectrum of a RO-based ADC are proposed theoretically. In particular, a quadrature RO-based band-pass ADC and a power-efficient Nyquist A/D converter are proposed and validated by simulations. All the techniques proposed in this work are especially devoted for highbandwidth applications, such as Internet-of-Things (IoT) nodes or maximally digital radio receivers. Nevertheless, their field of application is not restricted to them, and could be extended to others like biomedical instrumentation or sensing.El propósito de esta tesis doctoral es la propuesta y la implementación de arquitecturas de conversión de datos basadas en osciladores en anillos, compatibles con diseños mayoritariamente digitales, escalables en los procesos CMOS de fabricación más modernos donde las estructuras digitales se ven favorecidas. La miniaturización de las tecnologías CMOS de diseño lleva consigo la reducción de la tensión de alimentación para el desarrollo de arquitecturas pequeñas y eficientes en potencia. Esto reduce significativamente la disponibilidad de tensión para saturar transistores, lo que añadido a una ganancia cada vez menor de los mismos, ruido y efectos parásitos como el “mismatch” y las variaciones de proceso, tensión y temperatura han llevado a que sea cada vez más complejo el diseño de estructuras analógicas eficientes. Durante los últimos años la conversión A/D basada en codificación temporal ha ganado gran popularidad dado que permite la implementación de estructuras mayoritariamente digitales. Como parte de esta evolución, los osciladores controlados por tensión diseñados con topologías de oscilador en anillo han surgido como un candidato prometedor para la concepción de nuevas técnicas de digitalización. Los convertidores de datos basados en osciladores en anillo son extremadamente sensibles (variación de frecuencia con respecto a la señal de entrada) así como escalables, además de otras propiedades muy atractivas, como el conformado espectral de ruido de cuantificación y el filtrado “anti-aliasing”. Sin embargo, su respuesta no lineal y el limitado tiempo de retraso alcanzable por una compuerta NOT restringen la resolución del conversor, especialmente para conversión A/D en aplicaciones de elevado ancho de banda. Esta tesis doctoral propone nuevas técnicas para aliviar este tipo de problemas. En primer lugar, se proponen técnicas basadas en circuito para compensar el efecto de la no linealidad en los osciladores en anillo, y se comparan con soluciones equivalentes ya publicadas. Las propuestas se diseñan y simulan en tecnología CMOS de 65 nm para arquitecturas en lazo abierto. Una de estas técnicas presentadas es también validada experimentalmente a través de un prototipo. En segundo lugar, se introducen y validan por simulación varias formas de incrementar artificialmente la frecuencia de oscilación efectiva. Para finalizar, se proponen teóricamente dos enfoques para configurar nuevas formas de conformación del ruido de cuantificación y filtrado del espectro de salida de los datos digitales. En particular, son propuestos y validados por simulación un ADC pasobanda en cuadratura de fase y un ADC de Nyquist de gran eficiencia en potencia. Todas las técnicas propuestas en este trabajo están destinadas especialmente para aplicaciones de alto ancho de banda, tales como módulos para el Internet de las cosas o receptores de radiofrecuencia mayoritariamente digitales. A pesar de ello, son extrapolables también a otros campos como el de la instrumentación biomédica o el de la medición de señales mediante sensores.Programa de Doctorado en Ingeniería Eléctrica, Electrónica y Automática por la Universidad Carlos III de MadridPresidente: Juan Pablo Alegre Pérez.- Secretario: Celia López Ongil.- Vocal: Fernando Cardes Garcí

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery

Theory and applications of delta-sigma analogue-to-digital converters without negative feedback

Analog-to-digital converters play a crucial role in modern audio and communication design. Conventional Nyquist converters are suitable only for medium resolutions and require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can achieve high resolutions (>20bits) and can be implemented using straightforward, high-tolerance analog components. In conventional oversampled modulators, negative feedback is applied in order to control the dynamic behavior of a system and to realize the attenuation of the quantization noise in the signal band due to noise shaping. However, feedback can also introduce undesirable effects such as limit cycles, jitter problems in continuous-time topologies, and infinite impulse responses. Additionally, it increases the system complexity due to extra circuit components such as nonlinear multi-bit digital-to-analog converters in the feedback path. Moreover, in certain applications such as wireless, biomedical sensory, or microphone implementations feedback cannot be applied. As a result, the main goal of this thesis is to develop sigma-delta data converters without feedback. Various new delta-sigma analog-to-digital converter topologies are explored their mathematical models are presented. Simulations are carried out to validate these models and to show performance results. Specifically, two topologies, a first-order and a second-order oscillator-based delta-sigma modulator without feedback are described in detail. They both can be implemented utilizing VCOs and standard digital gates, thus requiring only few components. As proof of concept, two digital microphones based on these delta-sigma converters without feedback were implemented and experimental results are given. These results show adequate performance and provide a new approach of measuring

Design and Implementation of Internal Model Based Controllers for DC/ AC Power Converters

The aim of this thesis is to design and implement an advanced control system for a working three-phase DC to AC power converter. Compared to' the traditional PI controller used widely in industry, the new voltage controller can track the reference voltage with improved accuracy and efficiency in the presence of different kind of local loads, and also works well in the single phase voltage control. This voltage controller is combined with a power controller to yield a complete controller. An important aspect of this work is the hardware implementation of the whole system. Main parts ofthis thesis are: ???????? 1. Review ofH-infinity and repetitive control techniques and their applications in power converters. 2. Design of a new voltage controller to eliminate the DC component in the output voltages, and taking into account the practical issues such as the processing delay due to the digital signal processor (DSP) implementation. 3. Modelling and simulation of the converter system incorporating different control techniques and with different kinds of loads. 4. Hardware implementation and the two-processor controller. The parallel communication between the DSPs. 5. The main problems encountered in???????????????????? hardware implementation and programming. The software used to initialize DSPs, implement the discretetime voltage controller and other functions such ~ generations of space vector pulse width modulation (SVPWM) signals, circuit protections, analog to digital (AD) cOl)versions, data transmission, etc. 6. Experimental results the under circumstances of no load connected to the converter, pure three-phase resistive loads, three-phase unbalanced resistive' loads and the series resistor-inductor loads. /Imperial Users onl

Comparative analysis between different approaches for single-phase PLLs

"In press"This paper presents a comparative analysis between two distinct synchronizing circuits, which are usually applied as the core of control algorithms for single-phase power quality applications. One of these synchronizing circuits corresponds to a single-phase Phase-Locked Loop (PLL), implemented in α-β coordinates (αβ-PLL), whereas the other one corresponds to the Enhanced PLL (E-PLL). The major contribution of this paper is to present a single-phase PLL oriented to power quality applications, with a very simple structure, capable to be synchronized with the fundamental component of an input signal (voltage or current), even considering substantial disturbances, such as, frequency deviations, phase shifts, harmonic components and amplitude variations. Simulation and experimental results, involving these two synchronizing circuits submitted to three different test cases, are provided in order to compare their transient and steady-state performance. Moreover, it is also presented a comparison involving the processing speed and memory requirements of these synchronizing circuits in the DSP TMS320F28335

Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Wide-bandwidth high-resolution search for extraterrestrial intelligence

Research accomplished during the third 6-month period is summarized. Research covered the following: dual-horn antenna performance; high electron mobility transistors (HEMT) low-noise amplifiers; downconverters; fast Fourier transform (FFT) array; and backend 'feature recognizer' array

Robust low power CMOS methodologies for ISFETs instrumentation

I have developed a robust design methodology in a 0.18 [Mu]m commercial CMOS process to circumvent the performance issues of the integrated Ions Sensitive Field Effect Transistor (ISFET) for pH detection. In circuit design, I have developed frequency domain signal processing, which transforms pH information into a frequency modulated signal. The frequency modulated signal is subsequently digitized and encoded into a bit-stream of data. The architecture of the instrumentation system consists of a) A novel front-end averaging amplifier to interface an array of ISFETs for converting pH into a voltage signal, b) A high linear voltage controlled oscillator for converting the voltage signal into a frequency modulated signal, and c) Digital gates for digitizing and differentiating the frequency modulated signal into an output bit-stream. The output bit stream is indistinguishable to a 1st order sigma delta modulation, whose noise floor is shaped by +20dB/decade. The fabricated instrumentation system has a dimension of 1565 [Mu] m 1565 [Mu] m. The chip responds linearly to the pH in a chemical solution and produces a digital output, with up to an 8-bit accuracy. Most importantly, the fabricated chips do not need any post-CMOS processing for neutralizing any trapped-charged effect, which can modulate on-chip ISFETs’ threshold voltages into atypical values. As compared to other ISFET-related works in the literature, the instrumentation system proposed in this thesis can cope with the mismatched ISFETs on chip for analogue-to-digital conversions. The design methodology is thus very accurate and robust for chemical sensing

Nonlinear Analysis and Control of Interleaved Boost Converter Using Real-Time Cycle to Cycle Variable Slope Compensation

Switched-mode power converters are inherently nonlinear and piecewise smooth systems that may exhibit a series of undesirable operations that can greatly reduce the converter's efficiency and lifetime. This paper presents a nonlinear analysis technique to investigate the influence of system parameters on the stability of interleaved boost converters. In this approach, Monodromy matrix that contains all the comprehensive information of converter parameters and control loop can be employed to fully reveal and understand the inherent nonlinear dynamics of interleaved boost converters, including the interaction effect of switching operation. Thereby not only the boundary conditions but also the relationship between stability margin and the parameters given can be intuitively studied by the eigenvalues of this matrix. Furthermore, by employing the knowledge gained from this analysis, a real-Time cycle to cycle variable slope compensation method is proposed to guarantee a satisfactory performance of the converter with an extended range of stable operation. Outcomes show that systems can regain stability by applying the proposed method within a few time periods of switching cycles. The numerical and analytical results validate the theoretical analysis, and experimental results verify the effectiveness of the proposed approach

Design of a low-cost high speed data capture card for the Hubble Sphere Hydrogen Survey

Includes bibliographical references (leaves 101-105).This thesis describes the design and implementation of a low-cost high speed data capture card for the Hubble Sphere Hydrogen Survey (HSHS). The Hubble Space Hydrogen Survey was initiated in an effort to build a low-cost cylindrical radio telescope for an all sky redshift survey with the observational goal to produce a 3-dimensional mapping of the bulk Hubble Sphere using Hydrogen 21cm emissions. This dissertation ï¬ rst investigates the system design to see how each of the user speciï¬ cations set by the planning team could be achieved in terms of design decisions, component selection and schematic capture. The final design. AstroGIG, satisï¬ es the user speciï¬ cations by capturing data up to a full power bandwidth of 1.7GHz with an instantaneous bandwidth of ≤ 250MHz white maximizing the dynamic range. AstroGIG buffers, processes, stores and ï¬ nally transmits the data through a 4-lane PCI-Express interface to a standard PC where the majority of the processing is performed. The system implementation is then described where issues relating to the process of transforming schematics into a physical PCB, and HSHS integration are discussed. The design is veriï¬ ed through Hyperlynx simulations to give a high degree of certainty that physical implementation and production would be successful. Results from tests on the actual hardware characterizing the overall system performance are presented. Conclusions are drawn based on these results and suggestions for future work and design improvements are recommended