Characterization and design of CMOS components for microwave and millimeter wave applications

Ph.DDOCTOR OF PHILOSOPH

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Plasmonic-Organic and Silicon-Organic Hybrid Modulators for High-Speed Signal Processing

High-speed electro-optic (EO) modulators are key devices for optical communications, microwave photonics, and for broadband signal processing. Among the different material platforms for high-density photonic integrated circuits (PIC), silicon photonics sticks out because of CMOS foundries specialized in PIC fabrication. However, the absence of the Pockels effect in silicon renders EO modulators with high-efficiency and large modulation bandwidth difficult. In this dissertation, plasmonic and photonic slot waveguide modulators are investigated. The devices are built on the silicon platform and are combined with highly-efficient organic EO materials. Using such a hybrid platform, we realize compact and fast plasmonic-organic hybrid (POH) and silicon-organic hybrid (SOH) modulators. As an application example, we demonstrate for the first time an advanced terahertz communication link by directly converting data on a 360 GHz carrier to a data stream on an optical carrier. For optical transmitter applications, we overcome the bandwidth limitation of conventional SOH modulators by introducing a high-k dielectric microwave slotline for guiding the modulating radio-frequency signal which is capacitively-coupled to the EO modulating region. We confirm the viability of such capacitively-coupled SOH modulators by generating four-state pulse amplitude modulated signals with data rates up to 200 Gbit/s

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Low Power Filtering Techniques for Wideband and Wireless Applications

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2

Low-power double-sampled delta-sigma modulator for broadband applications

High speed and high resolution analog-to-digital converter is a key building block for broadband wireless communications, high definition video applications, medical images and so on. By leveraging the down scaling of the latest CMOS technology and the noise shaping properties, delta-sigma (ΔΣ) ADCs are able to achieve wide-band operation and high accuracy simultaneously. At first in this thesis, two novel techniques which can be applied to high performance ΔΣ ADC design are proposed. The first one is a modulator architectural innovation that is able to effectively solve the feedback timing constraints in a double-sampled ΔΣ modulator. The second one is a transistor level improvement to reduce the hardware consumption in a standard Date Weighted Averaging (DWA) realization. Next, charge-pump (CP) based switched-capacitor (SC) integrator is discussed. A cross-coupling technique is proposed to eliminate parasitic capacitor effect in a CP based SC integrator. Also design methodologies are introduced to incorporate a modified CP based SC integrator into a low-distortion ΔΣ modulator. A second-order ΔΣ modulator was designed and simulated to verify the proposed modulator topology. Finally, design of a double-sampled broadband 12-bit ΔΣ modulator is presented. To achieve very low power consumption, this modulator utilizes the following two key design techniques: 1. Double sampled integrator to increase the effective over-sampling ratio. 2. Capacitor reset technique allows the use of only one feedback DAC at the front end of the modulator to completely eliminate the quantization noise folding back. A 2+2 cascaded topology with 3-bit internal quantizer is used in this ΔΣ modulator to adequately suppress the quantization noise while guarantee the loop stability. This ΔΣ modulator was fabricated in a 90nm digital CMOS process and achieves an SNDR of 70dB within a 5MHz signal bandwidth. The modulator occupies a silicon area of 0.5mm² and consumes 10mW with a supply voltage of 1.2V

Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS

Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.Postprint (published version

Analog-to-digital converter circuit and system design to improve with CMOS scaling

textThere is a need to rethink the design of analog/mixed-signal circuits to be viable in state-of-the-art nanometer-scale CMOS processes due to the hostile environment they create for analog circuits. Reduced supply voltages and smaller capacitances are beneficial to circuit speed and digital circuit power efficiency; however, these changes along with smaller dimensions and close coupling of fast-switching digital circuits have made high-accuracy voltage domain analog processing increasingly difficult. In this work, techniques to improve analog-to-digital converters (ADC) for nanometer-scale processes are explored. First, I propose a mostly-digital time-based oversampling delta-sigma (∆Σ) ADC architecture. This system uses time, rather than voltage, as the analog variable for its quantizer, where the noise shaping process is realized by modulating the width of a variable-width digital "pulse." The merits of this architecture render it not only viable to scaling, but also enable improved circuit performance with ever-increasing time resolution of scaled CMOS processes. This is in contrast to traditional voltage-based analog circuit design, whose performance generally decreases with scaling due to increasingly higher voltage uncertainty due to supply voltage reduction and short-channel effects. In conjunction with Dr. Woo Young Jung while he was a Ph.D. student at The University of Texas at Austin, two prototype implementations of the proposed architecture were designed and fabricated in TSMC 180 nm CMOS and IBM 45 nm Silicon-On-Insulator (SOI) processes. The prototype ADCs demonstrate that the architecture can achieve bandwidths of 5-20 MHz and ∼50 dB SNR with very small area. The first generation ADC core occupies an area of only 0.0275 mm² , while the second generation ADC core occupies 0.0192 mm² . The two prototypes can be categorized as some of the smallestarea modulators in the literature. Second, I analyze the measured results of the prototype ADC chips, and determine the source for the harmonic distortion. I then demonstrate a digital calibration algorithm that sufficiently mitigates the distortion. This calibration approach falls in the general philosophy of digitally-assisted analog systems. In this philosophy, digital calibration and post-correction are favored over traditional analog solutions, in which there is a high cost to the analog solution either in complexity, power, or area.Electrical and Computer Engineerin