On chip interconnects for multiprocessor turbo decoding architectures

International audienc

State-of-the-art in Power Line Communications: from the Applications to the Medium

In recent decades, power line communication has attracted considerable attention from the research community and industry, as well as from regulatory and standardization bodies. In this article we provide an overview of both narrowband and broadband systems, covering potential applications, regulatory and standardization efforts and recent research advancements in channel characterization, physical layer performance, medium access and higher layer specifications and evaluations. We also identify areas of current and further study that will enable the continued success of power line communication technology.Comment: 19 pages, 12 figures. Accepted for publication, IEEE Journal on Selected Areas in Communications. Special Issue on Power Line Communications and its Integration with the Networking Ecosystem. 201

A unified approach for managing heterogeneous processing elements on FPGAs

FPGA designs do not typically include all available processing elements, e.g., LUTs, DSPs and embedded cores. Additional work is required to manage their different implementations and behaviour, which can unbalance parallel pipelines and complicate development. In this paper we introduce a novel management architecture to unify heterogeneous processing elements into compute pools. A pool formed of E processing elements, each implementing the same function, serves D parallel function calls. A call-and-response approach to computation allows for different processing element implementations, connections, latencies and non-deterministic behaviour. Our rotating scheduler automatically arbitrates access to processing elements, uses greatly simplified routing, and scales linearly with D parallel accesses to the compute pool. Processing elements can easily be added to improve performance, or removed to reduce resource use and routing, facilitating higher operating frequencies. Migrating to larger or smaller FPGAs thus comes at a known performance cost. We assess our framework with a range of neural network activation functions (ReLU, LReLU, ELU, GELU, sigmoid, swish, softplus and tanh) on the Xilinx Alveo U280

Why Max-min Fairness Is Not Suitable For Multi-Hop Wireless Networks

We consider the issue of which criteria to use when evaluating the design of a wireless multihop network. It is known, and we illustrate in this paper, that maximizing the total capacity, or transport capacity, leads to gross imbalance and is not suitable. An alternative, which is often used in networking, is to consider the max-min fair allocation of rates, or of transport rates per node. We apply max-min fairness to the class of wireless, multi-hop networks for which the rate of a wireless link is an increasing functions of signal-to-noise ratio. This class includes CDMA and UWB. We show that, for a network in this class, the max-min fair allocation of bit or transport rates always gives the same rate to all flows. We show on one example that such an allocation is highly undesirable when the network is asymmetric. Another form of fairness, utility fairness, does not appear to have the same problem

A mathematical programming approach to stochastic and dynamic optimization problems

Includes bibliographical references (p. 46-50).Supported by a Presidential Young Investigator Award. DDM-9158118 Supported by matching funds from Draper Laboratory.Dimitris Bertsimas

Parameterization of Tensor Network Contraction

We present a conceptually clear and algorithmically useful framework for parameterizing the costs of tensor network contraction. Our framework is completely general, applying to tensor networks with arbitrary bond dimensions, open legs, and hyperedges. The fundamental objects of our framework are rooted and unrooted contraction trees, which represent classes of contraction orders. Properties of a contraction tree correspond directly and precisely to the time and space costs of tensor network contraction. The properties of rooted contraction trees give the costs of parallelized contraction algorithms. We show how contraction trees relate to existing tree-like objects in the graph theory literature, bringing to bear a wide range of graph algorithms and tools to tensor network contraction. Independent of tensor networks, we show that the edge congestion of a graph is almost equal to the branchwidth of its line graph