Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work

Electrical and Thermomechanical Co-Simulation Platform for NPP

Publisher Copyright: © 2021 by the authors. Licensee MDPI, Basel, Switzerland.In order to analyze the safety of nuclear power plants (NPP), interactions between ther-momechanical and automation processes, the on-site electrical grid, and the off-site transmission system should be studied in detail. However, an initial survey of simulation tools used for the modelling and simulation of NPP shows that existing simulation tools have some drawbacks in properly simulating the aforementioned interactions. In fact, they simulate detailed electrical power systems and thermomechanical systems but neglect the detailed interactions of the electrical system with thermomechanical and automation processes. To address this challenge, this paper devel-ops an open-source co-simulation platform which connects Apros, a proprietary simulator of the thermomechanical and automation processes in NPP, to power system simulators. The proposed platform provides an opportunity to simulate both the electrical and thermomechanical systems of an NPP simultaneously, and study the interactions between them without neglecting any details. This detailed analysis can identify critical faults more accurately, and provides better support for probabilistic risk analyses (PRA) of NPP. To investigate the effectiveness of the proposed platform, detailed thermomechanical and electrical models of an NPP, located in Finland, are cosimulated. The preliminary results emphasize that neglecting the detailed interactions between domains of NPP may lead to inaccurate simulation results and may affect NPP safety.Peer reviewe

An approach to design smart grids and their IT system by cosimulation

International audienceSmart grids are the oncoming generation of power grids, which rely on information and communication technologies to tackle decentralized and intermittent energy sources such as wind farms and photovoltaic plants. They integrate electronics, software information processing and telecommunications technical domains. Therefore the design of smart grids is complex because of the various technical domains and modeling tools at stake. In this article, we present an approach to their design, which relies on model driven engineering, executable models and FMI based cosimulation. This approach is illustrated on the use case of an insular power grid and allows to study the impact of power production decision

Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability