Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

Low-Power Wake-Up Receivers

The Internet of Things (IoT) is leading the world to the Internet of Everything (IoE), where things, people, intelligent machines, data and processes will be connected together. The key to enter the era of the IoE lies in enormous sensor nodes being deployed in the massively expanding wireless sensor networks (WSNs). By the year of 2025, more than 42 billion IoT devices will be connected to the Internet. While the future IoE will bring priceless advantages for the life of mankind, one challenge limiting the nowadays IoT from further development is the ongoing power demand with the dramatically growing number of the wireless sensor nodes. To address the power consumption issue, this dissertation is motivated to investigate low-power wake-up receivers (WuRXs) which will significantly enhance the sustainability of the WSNs and the environmental awareness of the IoT. Two proof-of-concept low-power WuRXs with focuses on two different application scenarios have been proposed. The first WuRX, implemented in a cost-effective 180-nm CMOS semiconductor technology, operates at 401−406-MHz band. It is a good candidate for application scenarios, where both a high sensitivity and an ultra-low power consumption are in demand. Concrete use cases are, for instance, medical implantable applications or long-range communications in rural areas. This WuRX does not rely on a further assisting semiconductor technology, such as MEMS which is widely used in state-of-the-art WuRXs operating at similar frequencies. Thus, this WuRX is a promising solution to low-power low-cost IoT. The second WuRX, implemented in a 45-nm RFSOI CMOS technology, was researched for short-range communication applications, where high-density conventional IoT devices should be installed. By investigation of the WuRX for operation at higher frequency band from 5.5 GHz to 7.5 GHz, the nowadays ever more over-traffic issues that arise at low frequency bands such as 2.4 GHz can be substantially addressed. A systematic, analytical research route has been carried out in realization of the proposed WuRXs. The thesis begins with a thorough study of state-of-the-art WuRX architectures. By examining pros and cons of these architectures, two novel architectures are proposed for the WuRXs in accordance with their specific use cases. Thereon, key WuRX parameters are systematically analyzed and optimized; the performance of relevant circuits is modeled and simulated extensively. The knowledge gained through these investigations builds up a solid theoretical basis for the ongoing WuRX designs. Thereafter, the two WuRXs have been analytically researched, developed and optimized to achieve their highest performance. Proof-of-concept circuits for both the WuRXs have been fabricated and comprehensively characterized under laboratory conditions. Finally, measurement results have verified the feasibility of the design concept and the feasibility of both the WuRXs

Design of adaptive analog filters for magnetic front-end read channels

Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem para canais de leitura em sistemas de gravação e reprodução de dados em suporte magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a 1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços muito significativos a nível mundial com o objectivo de se investigarem novas técnicas de realização de filtros em circuito integrado monolítico, especialmente em tecnologia CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização de soluções com as características desejadas. Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão de sinal bem como a escolha de bons modelos matemáticos para o tratamento da informação e a minimização de erro inerente às aproximações na conformidade aos princípios físicos dos dispositivos caracterizados. O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo, baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization) com base na igualização de sinal utilizando filtros integrados analógicos em tempo contínuo. Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo, dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa e análise de estruturas ideais no projecto de filtros recorrendo a representações no espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de circuitos de transcondutância para a implementação de filtros integrados analógicos em tempo contínuo. Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros no espaço de estados, correspondentes a duas soluções alternativas para a realização de um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem, para utilização num canal de leitura de dados em suporte magnético. Como parte constituinte destes filtros, apresenta-se uma técnica de realização de circuitos de transcondutância, e de realização de condensadores lineares usando matrizes de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se métodos de adaptação automática capazes de compensar os erros face aos valores nominais dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os quais apresentamos os resultados de simulação e de medição experimental obtidos. Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível de constituir uma solução para o controlo de posicionamento da cabeça de leitura em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo de igualação do canal de leitura. Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency filters. The motivation of this work was the search for filtering solutions for the readchannel in recording and reproduction of data on magnetic media systems, with costs and consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than the available circuits. Accordingly, as was done in this work, the rapid development of microelectronics technology raised very significant efforts worldwide in order to investigate new techniques for implementing such filters in monolithic integrated circuit, especially in CMOS technology (Complementary Metal Oxide Semiconductor). We present a comparative study on different hierarchical levels of the project, which led to the realization and characterization of solutions with the desired characteristics. In the first level, this study addresses the conceptual question of recording and transmission of signal and the choice of good mathematical models for the processing of information and minimization of error inherent in the approaches and in accordance with the principles of the characterized physical devices. The main work of this thesis is focused on the hierarchical levels of the architecture of the read channel and the integrated circuit implementation of its main block - the filtering block. At the architecture level of the read channel this work presents a comprehensive study on existing methodologies of adaptation and signal recovery of data on magnetic media. This project appears in the sequence of the proposed solution for a lowcost, low consumption, low voltage, low complexity, using CMOS digital technology for the performance of a DFE (Decision Feedback Equalization) based on the equalization of the signal using integrated analog filters in continuous time. At the project level of implementation of the filtering block and techniques for implementing filters and its building components, it was concluded that the technique based on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate for the implementation of very-high-frequency adaptive filters. We defined in this lower level, two sub-levels of depth study for this thesis, namely: research and analysis of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation of continuous time integrated analog filters. Following this study, we present and compare two filtering structures operating in the space of states, corresponding to two alternatives for achieving a realization of an adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a read-channel for magnetic media devices. As a constituent part of these filters, we present a technique for the realization of transconductance circuits and for the implementation of linear capacitors using arrays of MOSFET transistors for signal processing in very-high-frequency integrated circuits using sub-micrometric CMOS technology. We present methods capable of automatic adjustment and compensation for deviation errors in respect to the nominal values of the components inherent to the tolerances of the fabrication process, for which we present the simulation and experimental measurement results obtained. Also as a result of this study, is the presentation of a circuit that provides a solution for the control of the head positioning on recording/playback systems of data on magnetic media. The proposed block is an adaptive first-order filter, based on the same transconductance circuits and equalization techniques proposed and used in the implementation of the adaptive filter for the equalization of the read channel. This filter was designed and included in an integrated circuit (Jaguar) used to control the positioning of the read-head done for ATMEL company in Colorado Springs, and part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company

Transceiver architectures and sub-mW fast frequency-hopping synthesizers for ultra-low power WSNs

Wireless sensor networks (WSN) have the potential to become the third wireless revolution after wireless voice networks in the 80s and wireless data networks in the late 90s. This revolution will finally connect together the physical world of the human and the virtual world of the electronic devices. Though in the recent years large progress in power consumption reduction has been made in the wireless arena in order to increase the battery life, this is still not enough to achieve a wide adoption of this technology. Indeed, while nowadays consumers are used to charge batteries in laptops, mobile phones and other high-tech products, this operation becomes infeasible when scaled up to large industrial, enterprise or home networks composed of thousands of wireless nodes. Wireless sensor networks come as a new way to connect electronic equipments reducing, in this way, the costs associated with the installation and maintenance of large wired networks. To accomplish this task, it is necessary to reduce the energy consumption of the wireless node to a point where energy harvesting becomes feasible and the node energy autonomy exceeds the life time of the wireless node itself. This thesis focuses on the radio design, which is the backbone of any wireless node. A common approach to radio design for WSNs is to start from a very simple radio (like an RFID) adding more functionalities up to the point in which the power budget is reached. In this way, the robustness of the wireless link is traded off for power reducing the range of applications that can draw benefit form a WSN. In this thesis, we propose a novel approach to the radio design for WSNs. We started from a proven architecture like Bluetooth, and progressively we removed all the functionalities that are not required for WSNs. The robustness of the wireless link is guaranteed by using a fast frequency hopping spread spectrum technique while the power budget is achieved by optimizing the radio architecture and the frequency hopping synthesizer Two different radio architectures and a novel fast frequency hopping synthesizer are proposed that cover the large space of applications for WSNs. The two architectures make use of the peculiarities of each scenario and, together with a novel fast frequency hopping synthesizer, proved that spread spectrum techniques can be used also in severely power constrained scenarios like WSNs. This solution opens a new window toward a radio design, which ultimately trades off flexibility, rather than robustness, for power consumption. In this way, we broadened the range of applications for WSNs to areas in which security and reliability of the communication link are mandatory

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

Ultra Small Antenna and Low Power Receiver for Smart Dust Wireless Sensor Networks

Wireless Sensor Networks have the potential for profound impact on our daily lives. Smart Dust Wireless Sensor Networks (SDWSNs) are emerging members of the Wireless Sensor Network family with strict requirements on communication node sizes (1 cubic centimeter) and power consumption (< 2mW during short on-states). In addition, the large number of communication nodes needed in SDWSN require highly integrated solutions. This dissertation develops new design techniques for low-volume antennas and low-power receivers for SDWSN applications. In addition, it devises an antenna and low noise amplifier co-design methodology to increase the level of design integration, reduce receiver noise, and reduce the development cycle. This dissertation first establishes stringent principles for designing SDWSN electrically small antennas (ESAs). Based on these principles, a new ESA, the F-Inverted Compact Antenna (FICA), is designed at 916MHz. This FICA has a significant advantage in that it uses a small-size ground plane. The volume of this FICA (including the ground plane) is only 7% of other state-of-the-art ESAs, while its efficiency (48.53%) and gain (-1.38dBi) are comparable to antennas of much larger dimensions. A physics-based circuit model is developed for this FICA to assist system level design at the earliest stage, including optimization of the antenna performance. An antenna and low noise amplifier (LNA) co-design method is proposed and proven to be valid to design low power LNAs with the very low noise figure of only 1.5dB. To reduce receiver power consumption, this dissertation proposes a novel LNA active device and an input/ouput passive matching network optimization method. With this method, a power efficient high voltage gain cascode LNA was designed in a 0.13um CMOS process with only low quality factor inductors. This LNA has a 3.6dB noise figure, voltage gain of 24dB, input third intercept point (IIP3) of 3dBm, and power consumption of 1.5mW at 1.0V supply voltage. Its figure of merit, using the typical definition, is twice that of the best in the literature. A full low power receiver is developed with a sensitivity of -58dBm, chip area of 1.1mm2, and power consumption of 2.85mW