CMOS VLSI correlator design for radio-astronomical signal processing : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand

Multi-element radio telescopes employ methods of indirect imaging to capture the image of the sky. These methods are in contrast to direct imaging methods whereby the image is constructed from sensor measurements directly and involve extensive signal processing on antenna signals. The Square Kilometre Array, or the SKA, is a future radio telescope of this type that, once built, will become the largest telescope in the world. The unprecedented scale of the SKA requires novel solutions to be developed for its signal processing pipeline one of the most resource-consuming parts of which is the correlator. The SKA uses the FX correlator construction that consists of two parts: the F part that translates antenna signals into frequency domain and the X part that cross-correlates these signals between each other. This research focuses on the integrated circuit design and VLSI implementation issues of the X part of a very large FX correlator in 28 nm and 130 nm CMOS. The correlator’s main processing operation is the complex multiply-accumulation (CMAC) for which custom 28 nm CMAC designs are presented and evaluated. Performance of various memories inside the correlator also affects overall efficiency, and input-buffered and output-buffered approaches are considered with the goal of improving upon it. For output-buffered designs, custom memory control circuits have been designed and prototyped in 130 nm that improve upon eDRAM by taking advantage of sequential access patterns. For the input-buffered architecture, a new scheme is proposed that decreases the usage of the input-buffer memory by a third by making use of multiple accumulators in every CMAC. Because cross-correlation is a very data-intensive process, high-performance SerDes I/O is essential to any practical ASIC implementation. On the I/O design, the 28 nm full-rate transmitter delivering 15 Gbps per lane is presented. This design consists of the scrambler, the serialiser, the digital VCO with analog fine-tuning and the SST driver including features of a 4-tap FFE, impedance tuning and amplitude tuning

Electronics implementation of the solar neutron experiment

The electronic equipment design and function are discussed for the solar neutron counter experiment. Circuit diagrams are included

An Optimal Gate Design for the Synthesis of Ternary Logic Circuits

Department of Electrical EngineeringOver the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this thesis, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOS-based binary logic circuits and ternary device-based logic circuits We propose a methodology for using ternary values effectively in sequential logic. Proposed ternary D flip-flop is designed to normally operate in four-edges of a ternary clock signal. A quad-edge-triggered ternary D flip-flop (QETDFF) is designed with static gates using CNTFET. From HSPICE simulation results, we have confirmed that power-delay-product (PDP) of QETDFF is reduced by 82.31 % compared to state of the art ternary D flip-flop. We synthesize a ternary serial adder using QETDFF. PDP of the proposed ternary serial adder is reduced by 98.23 % compared to state of the art design.ope

Third order CMOS decimator design for sigma delta modulators

A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed

Introduction to Logic Circuits & Logic Design with Verilog

The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits were designed using classical techniques. Classical techniques relied heavily on manual design practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design style, academic textbooks were developed that taught classical digital design techniques. Around 1990, large-scale digital systems began being designed using hardware description languages (HDL) and automated synthesis tools. Broad-scale adoption of this modern design approach spread through the industry during this decade. Around 2000, hardware description languages and the modern digital design approach began to be taught in universities, mainly at the senior and graduate level. There were a variety of reasons that the modern digital design approach did not penetrate the lower levels of academia during this time. First, the design and simulation tools were difficult to use and overwhelmed freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid advances in programmable logic and design tools allowed the modern digital design approach to be implemented in a university setting, even in lower-level courses. This allowed students to learn the modern design approach based on HDLs and prototype their designs in real hardware, mainly fieldprogrammable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored, teaching hardware description languages and higher levels of design abstraction. This trend has continued until today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach the modern digital design approach move immediately into high-level behavioral modeling with minimal or no coverage of the underlying hardware used to implement the systems. As a result, students are not being provided the resources to understand the fundamental hardware theory that lies beneath the modern abstraction such as interfacing, gate-level implementation, and technology optimization. Students moving too rapidly into high levels of abstraction have little understanding of what is going on when they click the “compile and synthesize” button of their design tool. This leads to graduates who can model a breadth of different systems in an HDL but have no depth into how the system is implemented in hardware. This becomes problematic when an issue arises in a real design and there is no foundational knowledge for the students to fall back on in order to debug the problem

A programmable CMOS decimator for sigma-delta analog-to-digital converter and charge pump circuits

PROGRAMMABLE DECIMATOR FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER: In this work a programmable decimator design has been presented in 1.5 μm n-well CMOS process for integration with an existing modulator to form a sigma-delta analog-to-digital converter (ADC). The decimator is implemented using a second order Cascaded Integrator Comb (CIC) filter and can be programmed to work with two different oversampling ratios of 64 and 16. The input to the decimator is provided from a first order modulator. With oversampling ratios of 64 and 16, an output resolution of 10-bit and 7-bit, respectively are achieved for the ADC. The ADC can be operated with an oversampling clock frequency of up to 8 MHz and with an input signal bandwidth of up to 65 KHz. An in-built clock divider circuit has been designed which generates two output clocks whose frequencies are equal to the input clock frequency divided by the oversampling ratios 64 and 16. CHARGE PUMP CIRCUITS: The charge pump CMOS circuits are presented which are designed based on a new technique of internal clock voltage boosting. Four and six-stage charge pumps are implemented in 1.5 μm n-well CMOS process. The charge pump circuits can be operated in 1.2 V - 3 V power supply voltage range. Outputs of 12.5 V and 17.8 V are measured from four and six-stage charge pumps, respectively with a 3 V power supply. The charge pump circuits can also be used to generate clock voltages higher than the input clock voltage. In the present design, clock voltages of 8 V and 11 V have been generated from four-stage and six-stage charge pumps, respectively which are nearly 2.5 and 4 times the input clock voltage of 3 V. The technique of boosting the clock internally has been applied in implementation of a revised version of battery powered Bio-implantable Electrical Stimulation System (BESS) integrated circuit

Introduction to Logic Circuits & Logic Design with VHDL

The overall goal of this book is to fill a void that has appeared in the instruction of digital circuits over the past decade due to the rapid abstraction of system design. Up until the mid-1980s, digital circuits were designed using classical techniques. Classical techniques relied heavily on manual design practices for the synthesis, minimization, and interfacing of digital systems. Corresponding to this design style, academic textbooks were developed that taught classical digital design techniques. Around 1990, large-scale digital systems began being designed using hardware description languages (HDL) and automated synthesis tools. Broad-scale adoption of this modern design approach spread through the industry during this decade. Around 2000, hardware description languages and the modern digital design approach began to be taught in universities, mainly at the senior and graduate level. There were a variety of reasons that the modern digital design approach did not penetrate the lower levels of academia during this time. First, the design and simulation tools were difficult to use and overwhelmed freshman and sophomore students. Second, the ability to implement the designs in a laboratory setting was infeasible. The modern design tools at the time were targeted at custom integrated circuits, which are cost- and time-prohibitive to implement in a university setting. Between 2000 and 2005, rapid advances in programmable logic and design tools allowed the modern digital design approach to be implemented in a university setting, even in lower-level courses. This allowed students to learn the modern design approach based on HDLs and prototype their designs in real hardware, mainly field programmable gate arrays (FPGAs). This spurred an abundance of textbooks to be authored teaching hardware description languages and higher levels of design abstraction. This trend has continued until today. While abstraction is a critical tool for engineering design, the rapid movement toward teaching only the modern digital design techniques has left a void for freshman- and sophomore-level courses in digital circuitry. Legacy textbooks that teach the classical design approach are outdated and do not contain sufficient coverage of HDLs to prepare the students for follow-on classes. Newer textbooks that teach the modern digital design approach move immediately into high-level behavioral modeling with minimal or no coverage of the underlying hardware used to implement the systems. As a result, students are not being provided the resources to understand the fundamental hardware theory that lies beneath the modern abstraction such as interfacing, gate-level implementation, and technology optimization. Students moving too rapidly into high levels of abstraction have little understanding of what is going on when they click the “compile and synthesize” button of their design tool. This leads to graduates who can model a breadth of different systems in an HDL but have no depth into how the system is implemented in hardware. This becomes problematic when an issue arises in a real design and there is no foundational knowledge for the students to fall back on in order to debug the problem