Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication

25 years of network access technologies: from voice to internet; the changing face of telecommunications

This work contributes to knowledge in the field of semiconductor system architectures, circuit design and implementation, and communications protocols. The work starts by describing the challenges of interfacing legacy analogue subscriber loops to an electronic circuit contained within the Central Office (Telephone Exchange) building. It then moves on to describe the globalisation of the telecom network, the demand for software programmable devices to enable system customisation cost effectively, and the creation of circuit and system blocks to realise this. The work culminates in the application challenges of developing a wireless RF front end, including antenna, for an Ultra Wideband communications systems applications. This thesis illustrates how higher levels of integration over the period of 1981 to 2010 have influenced the realisation of complex system level products, particularly analogue signal processing capabilities for communications applications. There have been many publications illustrating the impact of technology advancement from an economic or technology perspective. The thesis shows how technology advancement has impacted the physical realisation of semiconductor products over the period, at system, circuit, and physical implementation levels

이동통신 기기에 적합한 재구성이 가능한 다중대역 선형 CMOS 전력증폭기에 관한 연구

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 권영우.In this Dissertation, a study on multiband reconfigurable linear CMOS power amplifier (PA) is performed. Since a larger number of frequency bands is allocated for 3G/4G mobile communication standards nowadays, handset PAs are required to support the ever-increasing number of frequency bands. With the advent of high-speed wireless data transmission, handset PAs are also demanded to perform linear power amplification under the wide-band signal condition. Even though the CMOS technology has cost and size benefits, however, designing a watt-level linear CMOS PA is a challenging issue due to low breakdown voltage and nonlinear nature of the CMOS device. To resolve the issues above, this study presents two methods suitable for multiband (MB) linear CMOS PA: a reconfigurable MB matching structure and a linearization technique. The proposed MB structure shares a PA core to reduce the cost and size, and contains the power- and frequency-reconfigurable matching networks as well as the output path-selection function. Thus, it can perform the MB operation requiring multiple frequency bands and target output powers. The reconfiguration mechanism is quantitatively analyzed and experimentally demonstrated. The fabricated tri-band reconfigurable 3G UMTS PA using an InGaP/GaAs heterojunction bipolar transistor (HBT) process for practical handset application showed minimal efficiency degradation of less than 2% by multi-banding, compared with a single-band reference PA. For linearization of a CMOS PA, a phase-based linearization technique is presented. Since the PA nonlinearity is determined by the dynamic AM-AM and AM-PM, the two distortions should simultaneously be considered in linearization. Contrary to the previous works which have focused on the correction of AM-AM distortion by providing an envelope-dependent gate-bias, this work proposes an AM-PM linearizer using a varactor and an envelope-reshaping circuit. This linearizer helps the PA recover AM-AM distortion as well. To validate the usefulness of the proposed linearizer, 1.88 GHz and 0.9 GHz stacked-FET PAs using a 0.32-μm silicon-on-insulator (SOI) CMOS process were designed and fabricated. Measurement results showed that the fabricated 1.88 / 0.9 GHz linear CMOS PAs achieved linear efficiencies (meeting –39 dBc W-CDMA ACLR) of higher than 44 / 49%. Furthermore, a single-chain MB linear CMOS PA was implemented based on the proposed MB reconfiguration and linearization techniques. The fabricated MB PA, which has two outputs and covers five popular uplink UMTS/LTE bands (Band 1/2/4/5/8: 824 ~ 1980 MHz), showed minimal efficiency degradation (< 3.3%) compared to the single-band dedicated CMOS PA with W-CDMA efficiencies in excess of 40.7%. Finally, the signal-bandwidth limiting effect of the envelope-based linear CMOS PA is discussed and a solution is proposed. Due to the time delay during envelope-detection and shaping, a timing mismatch between the incoming RF signal and envelope-reshaped signal occurs, thus resulting in no linearization effect under wide-band signal (LTE 20 MHz or more) conditions. To resolve the problem, a group delay circuit with a compact size is employed and thus the linearization effect of the proposed phase-based linearizer is maintained up to 40 MHz LTE bandwidth.Abstract i Contents iii List of Tables vi List of Figures vii 1. Introduction 1 1.1 Motivation 1 1.2 Multiband PA Structure 4 1.3 Linearization of CMOS PA 6 1.4 Dissertation Organization 7 1.5 References 9 2. A Multiband Reconfigurable Power Amplifier for 3G UMTS Handset Applications 10 2.1 Introduction 10 2.2 Operation Principle of the Reconfigurable Output Matching Network 12 2.2.1 Power Reconfigurable Network (PRN) 14 2.2.2 Frequency Reconfigurable Network (FRN) 17 2.2.3 Path Selection Network (PSN) 20 2.2.4 Experimental Validation of the PRN and FRN 24 2.3 Fabrication and Measurement of a MB UMTS Reconfigurable PA 26 2.3.1 Design 26 2.3.2 Measurement 31 2.4 Summary 37 2.5 References 38 3. Linearization of CMOS Power Amplifier and Its Multiband Application 41 3.1 Introduction 41 3.2 Linearization of CMOS PAs: Prior Arts 43 3.3 Harmonic Termination 46 3.3.1 Operation Analysis 47 3.3.2 Experimental Validation 52 3.4 Control of Gate Bias Modulation Effect 54 3.4.1 Analysis 54 3.4.2 Experimental Validation 60 3.5 Proposed Linearization #1: Hybrid Bias 67 3.6 Proposed Linearization #2: Phase Injection 71 3.6.1 Motivation 71 3.6.2 Phase (Capacitance) Injection 72 3.7 Linear CMOS PA Design 75 3.7.1 Baseline PA Design 76 3.7.2 Linearizer Design 78 3.7.3 Fabrication 82 3.8 Measurement Results 83 3.8.1 CW Measurement 83 3.8.2 W-CDMA Measurement 84 3.8.3 LTE Measurement 87 3.9 A Single-Chain MB Reconfigurable Linear PA in SOI CMOS 90 3.9.1 MB Linear CMOS PA: Design 90 3.9.2 MB Linear CMOS PA: Measurement 94 3.10 Summary 99 3.11 References 100 4. Linearization of CMOS Power Amplifier Convering Wideband Signal 105 4.1 Introduction 105 4.2 Bandwidth Limitation of Envelope-Based Linearizers 106 4.2.1 Analysis 106 4.2.2 Delay Correction 110 4.2.3 Feedforward Envelope-Detection Structure with a Delay T/L 114 4.3 Group Delay Circuit 117 4.3.1 Positive GDC versus Negative GDC 117 4.3.2 Left-Handed T/L-Based GDC 119 4.4 Fabrication and Measurement 122 4.4.1 GDC Measurement 123 4.4.2 LTE Measurement 124 4.5 Summary 127 4.6 References 128 5. Conclusions 130 5.1 Research Summary 130 5.2 Future Works 132 Abstract in Korean 133 Publications 135Docto

Broadband Power Amplifier Design with High Power, High Efficiency and Large Back-off Range

As modern communication system technology develops, the demand for devices with smaller size, higher efficiency, and larger bandwidth has increased dramatically. To achieve this purpose, a novel architecture of load modulated balanced amplifier (LMBA) with a unique load-modulation characteristic different from any existing LMBAs and Doherty power amplifiers (DPAs) was presented, which is named as Pseudo-Doherty LMBA (PD-LMBA). Based on a special combination of control amplifier (carrier) and balanced amplifier (peaking) together with proper phase and amplitude controls, an optimal load-modulation behavior can be achieved for PD-LMBA leading to maximized efficiency over extended power back-off range. More importantly, the efficiency optimization can be achieved with only a static setting of phase offset at a given frequency, which greatly simplifies the complexity for phase control. Furthermore, the co-operations of the carrier and peaking amplifiers in PD-LMBA are fully de-coupled, thus lifting the fundamental bandwidth barrier imposed on Doherty-based active load modulation. However, since PD-LMBA has CA over-driving concerns, a new load-modulated power amplifier (PA) architecture, Asymmetric Load-Modulated Balanced Amplifier (ALMBA), is proposed based on PD-LMBA. And a subsequent improved type-continuous mode Hybrid Asymmetric Load Modulation Balanced Amplifier (H-ALMBA) has been developed. The two sub-amplifiers (BA1 and BA2) of the balanced topology in an LMBA are set as peaking amplifiers with different thresholds when cooperating with the control amplifier (CA) as the carrier, forming a hybrid load modulation behavior between Doherty and ALMBA. Compared to standard LMBA, the proposed H-ALMBA has a three-way load modulation with CA, BA1 and BA2 through proper amplitude control and phase alignment. Thus, this new mode offers extended power back-off range and enhanced back-off efficiency without suffering from difficulty and complexity in wideband design as imposed on three-way Doherty PAs. Based on comprehensive theoretical derivation and analysis, the proposed H-ALMBA is designed and implemented using commercial GaN transistors and wideband quadrature couplers. Moreover, the continuous-mode matching is applied to the carrier amplifier achieving a maximized wideband efficiency at power back-off. This is the first time that continuous mode and ALMBA have been used in combination, and very satisfactory results have been achieved, exhibiting the highest 10-dB output power back-off (OBO) drain efficiency (DE) ever reported for wideband load-modulation PAs. The developed prototype experimentally demonstrates wide bandwidth from 0.55-2.2 GHz. The measurement exhibits an efficiency of 63-82% at peak output power, 51-62% for 5-dB OBO, and 50-66% for 10-dB OBO within the design bandwidth. When stimulated by a 20-MHz long term evolution (LTE) signal with 10.5-dB peak to average power ratio (PAPR), a 50-55% average efficiency is measured over the entire bandwidth at an average output power around 33 dBm

An optical communications link

Includes bibliographical references.The thesis describes the development of a specification for, and prototypes of, an opto-electric voice communications link. The introductory sections deal with the generalised optical communications channel, the available hardware, and some of the research that has been done in the field. The information presented is used to motivate the type of system to be developed. The emphasis is placed on cost, though not as an overriding consideration. Modulation systems are examined, and frequency modulation of an m.f. subcarrier is chosen. The development of the practical system is covered in detail, in particular the receiver frontend circuitry. Considerable discrepancies between the design figures and actual measured performance are analysed, and their causes located. A practical mechanical design is presented, with suggested modifications for production. In conclusion, future developments in the field are examined

Assessment of monthly rain fade in the equatorial region at C & KU-band using measat-3 satellite links

C & Ku-band satellite communication links are the most commonly used for equatorial satellite communication links. Severe rainfall rate in equatorial regions can cause a large rain attenuation in real compared to the prediction. ITU-R P. 618 standards are commonly used to predict satellite rain fade in designing satellite communication network. However, the prediction of ITU-R is still found to be inaccurate hence hinder a reliable operational satellite communication link in equatorial region. This paper aims to provide an accurate insight by assessment of the monthly C & Ku-band rain fade performance by collecting data from commercial earth stations using C band and Ku-band antenna with 11 m and 13 m diameter respectively. The antennas measure the C & Ku-band beacon signal from MEASAT-3 under equatorial rain conditions. The data is collected for one year in 2015. The monthly cumulative distribution function is developed based on the 1-year data. RMSE analysis is made by comparing the monthly measured data of C-band and Ku-band to the ITU-R predictions developed based on ITU-R’s P.618, P.837, P.838 and P.839 standards. The findings show that Ku-band produces an average of 25 RMSE value while the C-band rain attenuation produces an average of 2 RMSE value. Therefore, the ITU-R model still under predicts the rain attenuation in the equatorial region and this call for revisit of the fundamental quantity in determining the rain fade for rain attenuation to be re-evaluated

Digital Front-End Signal Processing with Widely-Linear Signal Models in Radio Devices

Necessitated by the demand for ever higher data rates, modern communications waveforms have increasingly wider bandwidths and higher signal dynamics. Furthermore, radio devices are expected to transmit and receive a growing number of different waveforms from cellular networks, wireless local area networks, wireless personal area networks, positioning and navigation systems, as well as broadcast systems. On the other hand, commercial wireless devices are expected to be cheap, be relatively small in size, and have a long battery life. The demands for flexibility and higher data rates on one hand, and the constraints on production cost, device size, and energy efficiency on the other, pose difficult challenges on the design and implementation of future radio transceivers. Under these diametric constraints, in order to keep the overall implementation cost and size feasible, the use of simplified radio architectures and relatively low-cost radio electronics are necessary. This notion is even more relevant for multiple antenna systems, where each antenna has a dedicated radio front-end. The combination of simplified radio front-ends and low-cost electronics implies that various nonidealities in the remaining analog radio frequency (RF) modules, stemming from unavoidable physical limitations and material variations of the used electronics, are expected to play a critical role in these devices. Instead of tightening the specifications and tolerances of the analog circuits themselves, a more cost-effective solution in many cases is to compensate for these nonidealities in the digital domain. This line of research has been gaining increasing interest in the last 10-15 years, and is also the main topic area of this work. The direct-conversion radio principle is the current and future choice for building low-cost but flexible, multi-standard radio transmitters and receivers. The direct-conversion radio, while simple in structure and integrable on a single chip, suffers from several performance degrading circuit impairments, which have historically prevented its use in wideband, high-rate, and multi-user systems. In the last 15 years, with advances in integrated circuit technologies and digital signal processing, the direct-conversion principle has started gaining popularity. Still, however, much work is needed to fully realize the potential of the direct-conversion principle. This thesis deals with the analysis and digital mitigation of the implementation nonidealities of direct-conversion transmitters and receivers. The contributions can be divided into three parts. First, techniques are proposed for the joint estimation and predistortion of in-phase/quadrature-phase (I/Q) imbalance, power amplifier (PA) nonlinearity, and local oscillator (LO) leakage in wideband direct-conversion transmitters. Second, methods are developed for estimation and compensation of I/Q imbalance in wideband direct-conversion receivers, based on second-order statistics of the received communication waveforms. Third, these second-order statistics are analyzed for second-order stationary and cyclostationary signals under several other system impairments related to circuit implementation and the radio channel. This analysis brings new insights on I/Q imbalances and their compensation using the proposed algorithms. The proposed algorithms utilize complex-valued signal processing throughout, and naturally assume a widely-linear form, where both the signal and its complex-conjugate are filtered and then summed. The compensation processing is situated in the digital front-end of the transceiver, as the last step before digital-to-analog conversion in transmitters, or in receivers, as the first step after analog-to-digital conversion. The compensation techniques proposed herein have several common, unique, attributes: they are designed for the compensation of frequency-dependent impairments, which is seen critical for future wideband systems; they require no dedicated training data for learning; the estimators are computationally efficient, relying on simple signal models, gradient-like learning rules, and solving sets of linear equations; they can be applied in any transceiver type that utilizes the direct-conversion principle, whether single-user or multi-user, or single-carrier or multi-carrier; they are modulation, waveform, and standard independent; they can also be applied in multi-antenna transceivers to each antenna subsystem separately. Therefore, the proposed techniques provide practical and effective solutions to real-life circuit implementation problems of modern communications transceivers. Altogether, considering the algorithm developments with the extensive experimental results performed to verify their functionality, this thesis builds strong confidence that low-complexity digital compensation of analog circuit impairments is indeed applicable and efficient

Development and Characterization of a 171Yb+ Miniature Ion Trap Frequency Standard

This dissertation reports on the development of a low-power, high-stability miniature atomic frequency standard based on 171Yb+ ions. The ions are buffer-gas cooled and held in a linear quadrupole trap that is integrated into a sealed, getter-pumped vacuum package, and interrogated on the 12.6 GHz hyperfine transition. We hope to achieve a long-term fractional frequency stability of 10^-14 with a miniature clock that consumes only 50 mW of power and occupies a volume of 5 cm^3. I discuss our progress over several years of work on this project. We began by building a conventional tabletop clock to use as a test bed while developing several designs of miniature ion-trap vacuum packages, while also developing techniques for various aspects of the clock operation, including ion loading, laser and magnetic field stabilization, and a low power ion trap drive. The ion traps were modeled using boundary element software to assist with the design and parameter optimization of new trap geometries. We expect a novel trap geometry that uses a material new to ion traps to lead to an exceptionally small ion trap vacuum package in the next phase of the project. To achieve the long-term stability required, we have also considered the sensitivity of the clock frequency to magnetic fields. A study of the motion of the individual ions in a room-temperature cloud in the trap was performed with the purpose of understanding the effect of both spatially varying and constant magnetic fields on the clock resonance and therefore the operation of the clock. These effects were studied experimentally and theoretically for several traps. In summary, this dissertation is a contribution to the design, development, and testing of a 171Yb+ ion cloud frequency standard and related techniques, including analyses of trap geometries and parameters, modeling of the ion motion, and the practical operation of the clock.Comment: PhD Dissertatio