3,051 research outputs found
Energy efficiency of mmWave massive MIMO precoding with low-resolution DACs
With the congestion of the sub-6 GHz spectrum, the interest in massive
multiple-input multiple-output (MIMO) systems operating on millimeter wave
spectrum grows. In order to reduce the power consumption of such massive MIMO
systems, hybrid analog/digital transceivers and application of low-resolution
digital-to-analog/analog-to-digital converters have been recently proposed. In
this work, we investigate the energy efficiency of quantized hybrid
transmitters equipped with a fully/partially-connected phase-shifting network
composed of active/passive phase-shifters and compare it to that of quantized
digital precoders. We introduce a quantized single-user MIMO system model based
on an additive quantization noise approximation considering realistic power
consumption and loss models to evaluate the spectral and energy efficiencies of
the transmit precoding methods. Simulation results show that
partially-connected hybrid precoders can be more energy-efficient compared to
digital precoders, while fully-connected hybrid precoders exhibit poor energy
efficiency in general. Also, the topology of phase-shifting components offers
an energy-spectral efficiency trade-off: active phase-shifters provide higher
data rates, while passive phase-shifters maintain better energy efficiency.Comment: Published in IEEE Journal of Selected Topics in Signal Processin
NIKEL_AMC: Readout electronics for the NIKA2 experiment
The New Iram Kid Arrays-2 (NIKA2) instrument has recently been installed at
the IRAM 30 m telescope. NIKA2 is a state-of-art instrument dedicated to
mm-wave astronomy using microwave kinetic inductance detectors (KID) as
sensors. The three arrays installed in the camera, two at 1.25 mm and one at
2.05 mm, feature a total of 3300 KIDs. To instrument these large array of
detectors, a specifically designed electronics, composed of 20 readout boards
and hosted in three microTCA crates, has been developed. The implemented
solution and the achieved performances are presented in this paper. We find
that multiplexing factors of up to 400 detectors per board can be achieved with
homogeneous performance across boards in real observing conditions, and a
factor of more than 3 decrease in volume with respect to previous generations.Comment: 21 pages; 16 figure
Design and Validation of a Software Defined Radio Testbed for DVB-T Transmission
This paper describes the design and validation of a Software Defined Radio (SDR) testbed, which can be used for Digital Television transmission using the Digital Video Broadcasting - Terrestrial (DVB-T) standard. In order to generate a DVB-T-compliant signal with low computational complexity, we design an SDR architecture that uses the C/C++ language and exploits multithreading and vectorized instructions. Then, we transmit the generated DVB-T signal in real time, using a common PC equipped with multicore central processing units (CPUs) and a commercially available SDR modem board. The proposed SDR architecture has been validated using fixed TV sets, and portable receivers. Our results show that the proposed SDR architecture for DVB-T transmission is a low-cost low-complexity solution that, in the worst case, only requires less than 22% of CPU load and less than 170 MB of memory usage, on a 3.0 GHz Core i7 processor. In addition, using the same SDR modem board, we design an off-line software receiver that also performs time synchronization and carrier frequency offset estimation and compensation
Temporal and spatial combining for 5G mmWave small cells
This chapter proposes the combination of temporal processing through Rake combining based on direct sequence-spread spectrum (DS-SS), and multiple antenna beamforming or antenna spatial diversity as a possible physical layer access technique for fifth generation (5G) small cell base stations (SBS) operating in the millimetre wave (mmWave) frequencies. Unlike earlier works in the literature aimed at previous generation wireless, the use of the beamforming is presented as operating in the radio frequency (RF) domain, rather than the baseband domain, to minimise power expenditure as a more suitable method for 5G small cells. Some potential limitations associated with massive multiple input-multiple output (MIMO) for small cells are discussed relating to the likely limitation on available antennas and resultant beamwidth. Rather than relying, solely, on expensive and potentially power hungry massive MIMO (which in the case of a SBS for indoor use will be limited by a physically small form factor) the use of a limited number of antennas, complimented with Rake combining, or antenna diversity is given consideration for short distance indoor communications for both the SBS) and user equipment (UE). The proposal’s aim is twofold: to solve eroded path loss due to the effective antenna aperture reduction and to satisfy sensitivity to blockages and multipath dispersion in indoor, small coverage area base stations. Two candidate architectures are proposed. With higher data rates, more rigorous analysis of circuit power and its effect on energy efficiency (EE) is provided. A detailed investigation is provided into the likely design and signal processing requirements. Finally, the proposed architectures are compared to current fourth generation long term evolution (LTE) MIMO technologies for their anticipated power consumption and EE
A 10-bit Charge-Redistribution ADC Consuming 1.9 ÎĽW at 1 MS/s
This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 ÎĽm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 ÎĽW and achieves an energy efficiency of 4.4 fJ/conversion-step
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