721 research outputs found

    Analog Compressive Sensing for Multi-Channel Neural Recording: Modeling and Circuit Level Implementation

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    RÉSUMÉ Dans cette thĂšse, nous prĂ©sentons la conception d’un implant d’enregistrement neuronal multicanaux avec un Ă©chantillonnage compressĂ© mis en oeuvre avec un procĂ©dĂ© de fabrication CMOS Ă  65 nm. La rĂ©duction de la technologie a˙ecte Ă  la baisse les paramĂštres des amplificateurs neuronaux couplĂ©s en AC, comme la frĂ©quence de coupure basse, en raison de l’e˙et de canal court des transistors MOS. Nous analysons la frĂ©quence de coupure basse et nous constatons que l’origine de ce problĂšme, dans les technologies avancĂ©es, est la diminution de l’impĂ©dance d’entrĂ©e de l’amplificateur opĂ©rationnel de transconductance (OTA) en raison de la fuite d’oxyde de grille Ă  l’entrĂ©e des OTA. Nous proposons deux solutions pour rĂ©duire la frĂ©quence de coupure basse sans augmenter la valeur des condensateurs de rĂ©troaction de l’étage d’entrĂ©e. La premiĂšre solution est appelĂ©e rĂ©troaction positive croisĂ©e et la deuxiĂšme solution utilise des PMOS Ă  oxyde Ă©pais dans la paire de l’entrĂ©e di˙érentielle de l’OTA. Il est Ă  noter que pour compresser le signal neuronal, nous utilisons le CS dans le domaine analogique. Pour la rĂ©alisation, un intĂ©grateur Ă  capacitĂ© commutĂ©e est requis. Les paramĂštres non idĂ©aux de l’OTA utilisĂ© dans cet intĂ©grateur, tels que le gain fini, la bande passante, la vitesse de balayage et le changement rapide de la sortie. Toutes ces imperfections induisent des erreurs et rĂ©duisent le rapport signal sur bruit (SNR) total. Nous avons simulĂ© ces imperfections sur Matlab et Simulink pour dĂ©finir les spĂ©cifications de l’OTA requis. Aussi, pour concevoir les circuits analogiques correspondant aux interfaces neuronales requises, tels qu’un amplificateur neuronal, une rĂ©fĂ©rence de tension compacte et Ă  faible consommation d’énergie est requise. Nous avons proposĂ© une rĂ©fĂ©rence de tension de faible consommation d’énergie sans utiliser le transistor bipolaire parasite de la technologie CMOS pour diminuer la surface de silicium requise. Finalement, nous avons complĂ©tĂ© l’encodeur de CS et un convertisseur analogique-numĂ©rique Ă  approximation successive (SAR ADC) requis pour la chaine d’enregistrement des signaux neuronaux dans ce projet.----------ABSTRACT In this thesis we present the design of a multi-channel neural recording implant with analog compressive sensing (CS) in 65 nm process. Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cuto˙ frequency due to the short-channel e˙ects of MOS transistors. We analyze the low-cuto˙ frequency and find that the main reason of this problem in advanced technologies is decreasing the input resistance of the operational transconductance amplifier (OTA) due to the gate oxide static current leakage in the input of the OTA. In advanced technologies, the gate oxide is thin and some electrons can penetrate to the channel and cause DC current leakage. We proposed two solutions to reduce the low-cuto˙ frequency without increasing the value of the feedback capacitors of the front-end neural amplifier. The first solution is called cross-coupled positive feedback, and the second solution is utilizing thick-oxide PMOS transistors in the input di˙erential pair of the OTA. Compress the neural signal, we utilized the CS method in analog domain. For its implementation, a switched-capacitor integrator is required. Non-ideal specifications of OTA of CS integrator such as finite gain, bandwidth, slew rate and output swing induce error and reduce the total signal to noise ratio (SNR). We simulated these non-idealities in Matlab and Simulink and extracted the specification of the required OTA. Also, to design analog circuits such as neural amplifier a low power and compact voltage reference is required. We implemented a low-power band-gap reference without utilizing parasitic bipolar transis-tor to decrease the silicon area. At the end, we completed the CS encoder and successive approximation architecture analog-to-digital converter (SAR ADC)

    Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants

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    Implantable systems are nowadays being used to interface the human brain with external devices, in order to understand and potentially treat neurological disorders. The most predominant design constraints are the system’s area and power. In this paper, we implement and combine advanced compressive sampling algorithms to reduce the power requirements of wireless telemetry. Moreover, we apply variable compression, to dynamically modify the device performance, based on the actual signal need. This paper presents an area-efficient adaptive system for wireless implantable devices, which dynamically reduces the power requirements yielding compression rates from 8× to 64×, with a high reconstruction performance, as qualitatively demonstrated on a human data set. Two different versions of the encoder have been designed and tested, one with and the second without the adaptive compression, requiring an area of 230×235 ÎŒm and 200 × 190 ÎŒm, respectively, while consuming only 0.47 ÎŒW at 0.8 V. The system is powered by a 4-coil inductive link with measured power transmission efficiency of 36%, while the distance between the external and internal coils is 10 mm. Wireless data communication is established by an OOK modulated narrowband and an IR-UWB transmitter, while consuming 124.2 pJ/bit and 45.2 pJ/pulse, respectively

    Learning-Based Hardware Design for Data Acquisition Systems

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    This multidisciplinary research work aims to investigate the optimized information extraction from signals or data volumes and to develop tailored hardware implementations that trade-off the complexity of data acquisition with that of data processing, conceptually allowing radically new device designs. The mathematical results in classical Compressive Sampling (CS) support the paradigm of Analog-to-Information Conversion (AIC) as a replacement for conventional ADC technologies. The AICs simultaneously perform data acquisition and compression, seeking to directly sample signals for achieving specific tasks as opposed to acquiring a full signal only at the Nyquist rate to throw most of it away via compression. Our contention is that in order for CS to live up its name, both theory and practice must leverage concepts from learning. This work demonstrates our contention in hardware prototypes, with key trade-offs, for two different fields of application as edge and big-data computing. In the framework of edge-data computing, such as wearable and implantable ecosystems, the power budget is defined by the battery capacity, which generally limits the device performance and usability. This is more evident in very challenging field, such as medical monitoring, where high performance requirements are necessary for the device to process the information with high accuracy. Furthermore, in applications like implantable medical monitoring, the system performances have to merge the small area as well as the low-power requirements, in order to facilitate the implant bio-compatibility, avoiding the rejection from the human body. Based on our new mathematical foundations, we built different prototypes to get a neural signal acquisition chip that not only rigorously trades off its area, energy consumption, and the quality of its signal output, but also significantly outperforms the state-of-the-art in all aspects. In the framework of big-data and high-performance computation, such as in high-end servers application, the RF circuits meant to transmit data from chip-to-chip or chip-to-memory are defined by low power requirements, since the heat generated by the integrated circuits is partially distributed by the chip package. Hence, the overall system power budget is defined by its affordable cooling capacity. For this reason, application specific architectures and innovative techniques are used for low-power implementation. In this work, we have developed a single-ended multi-lane receiver for high speed I/O link in servers application. The receiver operates at 7 Gbps by learning inter-symbol interference and electromagnetic coupling noise in chip-to-chip communication systems. A learning-based approach allows a versatile receiver circuit which not only copes with large channel attenuation but also implements novel crosstalk reduction techniques, to allow single-ended multiple lines transmission, without sacrificing its overall bandwidth for a given area within the interconnect's data-path

    Ultrafast single-channel machine vision based on neuro-inspired photonic computing

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    High-speed machine vision is increasing its importance in both scientific and technological applications. Neuro-inspired photonic computing is a promising approach to speed-up machine vision processing with ultralow latency. However, the processing rate is fundamentally limited by the low frame rate of image sensors, typically operating at tens of hertz. Here, we propose an image-sensor-free machine vision framework, which optically processes real-world visual information with only a single input channel, based on a random temporal encoding technique. This approach allows for compressive acquisitions of visual information with a single channel at gigahertz rates, outperforming conventional approaches, and enables its direct photonic processing using a photonic reservoir computer in a time domain. We experimentally demonstrate that the proposed approach is capable of high-speed image recognition and anomaly detection, and furthermore, it can be used for high-speed imaging. The proposed approach is multipurpose and can be extended for a wide range of applications, including tracking, controlling, and capturing sub-nanosecond phenomena.Comment: 30 pages, 12 figure

    Optimized Biosignals Processing Algorithms for New Designs of Human Machine Interfaces on Parallel Ultra-Low Power Architectures

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    The aim of this dissertation is to explore Human Machine Interfaces (HMIs) in a variety of biomedical scenarios. The research addresses typical challenges in wearable and implantable devices for diagnostic, monitoring, and prosthetic purposes, suggesting a methodology for tailoring such applications to cutting edge embedded architectures. The main challenge is the enhancement of high-level applications, also introducing Machine Learning (ML) algorithms, using parallel programming and specialized hardware to improve the performance. The majority of these algorithms are computationally intensive, posing significant challenges for the deployment on embedded devices, which have several limitations in term of memory size, maximum operative frequency, and battery duration. The proposed solutions take advantage of a Parallel Ultra-Low Power (PULP) architecture, enhancing the elaboration on specific target architectures, heavily optimizing the execution, exploiting software and hardware resources. The thesis starts by describing a methodology that can be considered a guideline to efficiently implement algorithms on embedded architectures. This is followed by several case studies in the biomedical field, starting with the analysis of a Hand Gesture Recognition, based on the Hyperdimensional Computing algorithm, which allows performing a fast on-chip re-training, and a comparison with the state-of-the-art Support Vector Machine (SVM); then a Brain Machine Interface (BCI) to detect the respond of the brain to a visual stimulus follows in the manuscript. Furthermore, a seizure detection application is also presented, exploring different solutions for the dimensionality reduction of the input signals. The last part is dedicated to an exploration of typical modules for the development of optimized ECG-based applications

    A 32-Channel Time-Multiplexed Artifact-Aware Neural Recording System

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    This paper presents a low-power, low-noise microsystem for the recording of neural local field potentials or intracranial electroencephalographic signals. It features 32 time-multiplexed channels at the electrode interface and offers the possibility to spatially delta encode data to take advantage of the large correlation of signals captured from nearby channels. The circuit also implements a mixed-signal voltage-triggered auto-ranging algorithm which allows to attenuate large interferers in digital domain while preserving neural information. This effectively increases the system dynamic range and avoids the onset of saturation. A prototype, fabricated in a standard 180 nm CMOS process, has been experimentally verified in-vitro with cellular cultures of primary cortical neurons from mice. The system shows an integrated input-referred noise in the 0.5–200 Hz band of 1.4 ”Vrms for a spot noise of about 85 nV / √Hz. The system draws 1.5 ”W per channel from 1.2 V supply and obtains 71 dB + 26 dB dynamic range when the artifact-aware auto-ranging mechanism is enabled, without penalising other critical specifications such as crosstalk between channels or common-mode and power supply rejection ratios
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