110 research outputs found
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ΣΔ) modulators (ΣΔMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ΣΔM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 μW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ΣΔM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuit’s sensitivity to the circuit components’ variations. This continuous-time, 2-1 MASH ΣΔM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ΣΔM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the author’s knowledge the circuit achieves the lowest Walden FOMW for ΣΔMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
Oversampled analog-to-digital converter architectures based on pulse frequency modulation
Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development
of voltage-controlled oscillator based analog-to-digital converters (VCO-based
ADCs). Time-encoding based ADCs have become of great interest to the designer
community due to the possibility of implementing mostly digital circuits,
which are well suited for current deep-submicron CMOS processes. Within this
topic, VCO-based ADCs are one of the most promising candidates.
VCO-based ADCs have typically been analyzed considering the output phase
of the oscillator as a state variable, similar to the state variables considered in __
modulation loops. Although this assumption might take us to functional designs
(as verified by literature), it does not take into account neither the oscillation
parameters of the VCO nor the deterministic nature of quantization noise. To
overcome this issue, we propose an interpretation of these type of systems based
on the pulse frequency modulation (PFM) theory. This permits us to analytically
calculate the quantization noise, in terms of the working parameters of the system.
We also propose a linear model that applies to VCO-based systems. Thanks to
it, we can determine the different error processes involved in the digitization of
the input data, and the performance limitations which these processes direct to.
A generic model for any order open-loop VCO-based ADCs is made based on the
PFM theory. However, we will see that only the first-order case and a second order
approximation can be implemented in practice. The PFM theory also
allows us to propose novel approaches to both single-stage and multistage VCObased
architectures. We describe open-loop architectures such as VCO-based
architectures with digital precoding, PFM-based architectures that can be used
as efficient ADCs or MASH architectures with optimal noise-transfer-function
(NTF) zeros. We also make a first approach to the proposal and analysis of closed loop
architectures. At the same time, we deal with one of the main limitations of
VCOs (especially those built with ring oscillators), which is the non-linear voltage to-
frequency relation. In this document, we describe two techniques mitigate this
phenomenon.
Firstly, we propose to use a pulse width modulator in front of the VCO. This
way, there are only two possible oscillation states. Consequently, the oscillator
works linearly. To validate the proposed technique, an experimental prototype
was implemented in a 40-nm CMOS process. The chip showed noise problems
that degraded the expected resolution, but allowed us to verify that the potential
performance was close to the expected one. A potential signal-to-noise-distortion
ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming
2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar
power consumption and linearity properties.
Secondly, we used a pulse frequency modulator to implement a second ADC.
The proposed architecture is intrinsically linear and uses a digital delay line to
increase the resolution of the converter. One experimental prototype was implemented
in a 40-nm CMOS process using one of these architectures. Proper results
were measured from this prototype. These results allowed us to verify that the
PFM-based architecture could be used as an efficient ADC. The measured peak
SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an
occupied area equal to 0.08 mm2. The architecture shows a great linearity, and
in comparison to related work, it consumes less power and occupies similar area.
In general, the theoretical analyses and the architectures proposed in the
document are not restricted to any application. Nevertheless, in the case of the
experimental chips, the specifications required for these converters were linked to
communication applications (e.g. VDSL, VDSL2, or even G.fast), which means
medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low
area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva
para el diseño de convertidores analógico-digitales basados en osciladores
controlados por tensión. Los convertidores analógico-digitales con codificación
temporal han llamado la atención durante los últimos años de la comunidad de
diseñadores debido a la posibilidad de implementarlos en su gran mayoría con
circuitos digitales, los cuales son muy apropiados para los procesos de diseño
manométricos. En este ámbito, los convertidores analógico-digitales basados en
osciladores controlados por tensión son uno de los candidatos más prometedores.
Los convertidores analógico-digitales basados en osciladores controlados por
tensión han sido típicamente analizados considerando que la fase del oscilador
es una variable de estado similar a las que se observan en los moduladores __.
Aunque esta consideración puede llevarnos a diseños funcionales (como se puede
apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni
los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de
la modulación por frecuencia de pulsos. Esto nos permite calcular de forma
analítica las ecuaciones que modelan el ruido de cuantificación en función de los
parámetros de oscilación. Se propone también un modelo lineal para el análisis de
convertidores analógico-digitales basados en osciladores controlados por tensión.
Este modelo permite determinar las diferentes fuentes de error que se producen
durante el proceso de digitalización de los datos de entrada y las limitaciones
que suponen. Un modelo genérico de convertidor de cualquier orden se propone
con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una
aproximación al caso de segundo orden se pueden implementar en la práctica.
La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas
para la propuesta y el análisis tanto de arquitecturas de una sola etapa
como de arquitecturas de varias etapas construidas con osciladores controlados
por tensión. Se proponen y se describen arquitecturas en lazo abierto como son
las basadas en osciladores controlador por tensión con moduladores digitales en
la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como
convertidores analógico-digitales eficientes o arquitecturas en cascada en las que
se optimizan la distribución de los ceros en la función de transferencia del ruido.
También se realiza una aproximación a la propuesta y el análisis de arquitecturas
en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes
de los osciladores controlados por tensión (especialmente en aquellos
implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos
técnicas cuyo objetivo es mitigar esta limitación.
La primera técnica de corrección se basa en el uso de un modulador por
ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo
existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y
no se genera distorsión en los datos de salida. La técnica se propone de forma
teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo
la validación de la propuesta teórica se fabricó un prototipo experimental en un
proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la
resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá
haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una
potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de
banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con
sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo
que se mantiene el consumo así como la linealidad.
A continuación, se propone la implementación de un convertidor analógico digital
mediante un modulador por frecuencia de pulsos. La arquitectura propuesta
es intrínsecamente lineal y hace uso de una línea de retraso digital con
el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental,
se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura,
de la que se obtuvieron resultados notables. Estos resultados permitieron
verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor
analógico-digital eficiente. La arquitectura consigue una relación real
señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo
de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en
comparación con arquitecturas equivalentes, el consumo es menor mientras que
el área ocupada se mantiene similar.
En general, las aportaciones propuestas en este documento se pueden aplicar a
cualquier tipo de aplicación, independientemente de los requisitos de resolución,
ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos
fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones
(VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media
(9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja
área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman
Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications
Imperial Users onl
Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators
RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs
Recommended from our members
Wide-bandwidth, high-resolution delta-sigma analog-to-digital converters
There is a significant need in recent mobile communication and wireless broadband
systems for high-performance analog-to-digital converters (ADCs) that have wide
bandwidth (BW>5-MHz) and high data rate (>100-Mbps). A delta-sigma ADC is
recognized as a power-efficient ADC architecture when high resolution (>12-b) is
required. This is due to several advantages of the delta-sigma ADC including relaxed
anti-aliasing filter requirements, high signal-to-noise and distortion ratio (SNDR) and
most importantly, reduced sensitivity to analog imperfections. In this thesis, several
structures and design techniques are developed for the implementation of continuoustime
(CT) and discrete-time (DT) delta-sigma ADCs. These techniques save the total
power consumption, reduce the design complexity, and decrease the chip die area of
delta-sigma modulators.
First a 4th-order single stage CT delta-sigma ADC with a novel single-amplifier-biquad
(SAB) based loop filter is presented. By utilizing the SAB networks in the loop filter of
an Nth-order CT delta-sigma modulator, it requires only half the number of active
amplifiers and feed-forward branches used in the conventional modulator architecture,
thus decreasing the power consumption and area by reducing the number of amplifiers.
The proposed scheme also enables the modulator to use a switch-capacitor (SC) adder
due to the reduced number of feedforward branches to its summing block. As a sequence,
it consumes less power compared to a conventional CT adder. With a 130-nm CMOS
technology, the fabricated prototype IC achieves a dynamic range of 80 dB with 10 MHz
signal bandwidth and analog power dissipation lower than 12 mW. Presented as the
second scheme to save power consumption and chip die area in ΔΣ modulators is a new
stage-sharing technique in a discrete-time 2-2 MASH ΔΣ ADC. The proposed technique
shares all the active blocks of the modulator second stage with its first stage during the
two non-overlapping clock phases. Measurement results show that the modulator
designed in a 0.13-um CMOS technology achieves 76 dB SNDR over a 10 MHz
conversion bandwidth dissipating less than 9 mW analog power
Recommended from our members
Design of low OSR, high precision analog-to-digital converters
Advances in electronic systems have lead to the demand for high resolution, high bandwidth Analog-to-Digital Converters (ADCs). Oversampled ADCs are well- known for high accuracy applications since they benefit from noise shaping and they usually do not need highly accurate components. However, as a consequence of oversampling, they have limited signal bandwidth. The signal bandwidth (BW) of oversampled ADCs can be increased either by increasing the sampling rate or reducing the oversampling ratio (OSR). Reducing OSR is a more promising method for increasing the BW, since the sampling speed is usually limited by the technology. The advantageous properties (e.g. low in-band quantization, relaxed accuracy requirements of components) of oversampled ADCs are usually diminished at lower OSRs and preserving these properties requires complicated and power hungry architectures.
In this thesis, different combinations of delta-sigma and pipelined ADCs are explored and new techniques for designing oversampled ADCs are proposed. A Hybrid Delta-Sigma/Pipelined (HDSP) ADC is presented. This ADC uses a pipelined ADC as the quantizer of a single-loop delta-sigma modulator and benefits from
the aggressive quantization of the pipelined quantizer at low OSRs. A Noise-Shaped Pipelined ADC is proposed which exploits a delta-sigma modulator as the sub-ADC of a pipeline stage to reduce the sensitivity to the analog imperfection. Three prototype ADCs were fabricated in 0.18μm CMOS technology to verify the effectiveness of the proposed techniques. The performance of these architectures is among the best reported for high bandwidth oversampled ADCs.Keywords: Delta-Sigma, Loop Filter, Oversampled ADC, Gain Stage, Pipeline, Noise Shapin
Recommended from our members
Design techniques for low power ADCs
This dissertation presents an incremental analog-to-digital converter (ADC) with digital digital-to-analog converter (DAC) mismatch correction. A theoretical time-domain analysis technique was developed to predict the noise performance of the incremental ADC, and a new optimization technique was proposed to minimize the output noise.
In the calibration mode, the incremental ADC itself is used to measure the mismatches of the internal multi-bit DAC. Three new calibration techniques, equation-solving calibration, inter-DAC mismatch calibration and modified “Sarhang-Nejad” calibration are proposed.
To verify the above techniques, a test chip was designed and fabricated in 0.18 µm CMOS process. The chip can work in single-sampling or double-sampling mode. Chopping with a fractal sequence is used to eliminate 1/f noise. The calibration circuit was implemented to calibrate the multi-bit DAC mismatches the in single-sampling mode and inter-DAC mismatches in the double-sampling mode.
Finally, two new design techniques for low-power ADCs, the two-step split-junction successive-approximation register (SAR) ADC and the hybrid cascaded ∆Σ ADC, are proposed
Highly Linear 2,5-V CMOS ΣΔ Modulator for ADSL+
We present a 90-dB spurious-free dynamic range sigma–delta modulator (ΣΔM) for asymmetric digital subscriber line applications (both ADSL and ADSL+), with up to a 4.4-MS/s digital output rate. It uses a cascade (MASH) multibit architecture and has been implemented in a 2.5-V supply, 0.25μm CMOS process with metal–insulator–metal capacitors. The prototypes feature 78-dB dynamic range (DR) in the 30-kHz to 2.2-MHz band (ADSL+) and 85-dB DR in the 30-kHz to 1.1-MHz band (ADSL). Integral and differential nonlinearity are within +/-0.85 and +/-0.80 LSB, respectively. The ΣΔ modulator and its auxiliary blocks (clock phase and reference voltage generators, and I/O buffers) dissipate 65.8 mW. Only 55 mW are dissipated in the ΣΔ modulator.This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE.This work was supported by the European Union under IST Project 29261/MIXMODEST and IST Project 2001-34283/TAMES-2 and the Spanish MCyT and the ERDF under Project TIC2001-0929/ADAVERE.Peer reviewe
- …