Design-for-delay-testability techniques for high-speed digital circuits

The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays' circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and in particular the costs of Automatic Test Equipment are major concerns for the semiconductor industry. To reverse the trend of rising testing costs, DfDT is\ud getting more and more important

Doctor of Philosophy

dissertationThree major catastrophic failures in photovoltaic (PV) arrays are ground-faults, line-to-line faults, and arc faults. Although the number of such failures is few, recent fire events on April 5, 2009, in Bakersfield, California, and April 16, 2011, in Mount Holly, North Carolina suggest the need for improvements in present fault detection and mitigation techniques, as well as amendments to existing codes and standards to avoid such accidents. A fault prediction and detection technique for PV arrays based on spread spectrum time domain reflectometry (SSTDR) has been proposed and was successfully implemented. Unlike other conventional techniques, SSTDR does not depend on the amplitude of the fault-current. Therefore, SSTDR can be used in the absence of solar irradiation as well. However, wide variation in impedance throughout different materials and interconnections makes fault locating more challenging than prediction/detection of faults. Another application of SSTDR in PV systems is the measurement of characteristic impedance of power components for condition monitoring purposes. Any characteristic variations in one component will simultaneously alter the operating conditions of other components in a closed-loop system, resulting in a shift in overall reliability profile. This interdependence makes the reliability of a converter a complex function of time and operating conditions. Details of this failure mode, mechanism, and effect analysis (FMMEA) have been developed. By knowing the present state of health and the remaining useful life (RUL) of a power converter, it is possible to reduce the maintenance cost for expensive high-power converters by facilitating a reliability centered maintenance (RCM) scheme. This research is a step forward toward power converter reliability analysis since the cumulative effect of multiple degraded components has been considered here for the first time in order to estimate reliability of a power converter

Design and Test of Wide Input and Output Constant Current LED Driver

This senior project aims to provide design and test the performance of a DC-DC constant current LED driver for use in a larger DC smart building infrastructure. In this instance, a SEPIC topology is chosen to provide high efficiency output current at output voltages that can be above or below the input voltage. This is challenging since the same design must operate at similar efficiency for vastly different environmental conditions. As a part of a larger system, the design must be able to perform the given task consistently regardless of changes to the source and load power. The design uses the LT3795 LED controller to operate power switches and inductors to transform the input power into usable output power for a string of LEDs. The controller is paired with an onboard microcontroller to provide error reporting and supplement the PWM dimming control features of the IC. Simulations were done to ensure the efficiency of the design remained above 93% within the full range of input and output voltages, along with a range of PWM frequencies and duty cycles. After manufacturing and assembly, the board was found to be under specification regarding the input and output voltage ranges, as well as below the efficiency target. This was largely due to issues regarding the layout assembly of the finished product

Real-time monitoring and diagnostics of crystal-based collimation of particle accelerator beams

The beam collimation represents one of the important items for the future upgrade of the Large Hadron Collider (LHC) at CERN. An effective collimation system is particularly required at higher beam intensities, as even a relatively small number of particles impinging on the superconducting magnets can cause quenching (a sudden loss of superconducting condition). Although the currently used collimation system at CERN is working properly, it presents some limitations which can be overcome by future upgrades. One of these limitations is due the particle diffraction from heavy absorbers. An alternative option to the current collimation system at CERN is represented by the use of bent crystals. These latter are expected to be very effective in beam collimation. In fact, they have the advantage to guide halo particles of the beam on a single absorber. This allows the improvements to the cleaning performance as well as to the impedance of the collider as compared to the multi-stage collimation systems, consisting of large blocks made of amorphous material, placed around the beam. In this framework, UA9 Experiment at CERN is carrying on since many years an R&D on various types of crystals. The aim is to find the best solution to overcome the limitations of the currently used collimation system at CERN, in view of future upgrades of the collider. The first part of this PhD work has been devoted, within the UA9 collaboration, to the characterization of some new crystals to be used in LHC and in the Super Proton Synchrotron (SPS) for collimation. The radiation hardness for high energy neutrons were also tested for these crystals. Beam collimation monitoring is performed in the UA9 crystal based system using a Cherenkov detector for high energy protons going through the fused silica. Presently, classical PMTs are in use to collect the Cherenkov light, but its dark count rate is directly affected by the high intensity radiation. With the aim to face this limitation, the second part of this PhD project focused on the characterization of ZnO material, which resulted to be very promising for realizing alternative photodetectors. In this respect, Cherenkov detector/setup used in UA9 could be updated with more functional sensor systems which are radiation resistant and compatible with vacuum requirements in the beam pipe. Another important aspect in collimation systems is the real time monitoring of collimated beams inside the accelerators, especially when using a crystal based collimation system as in UA9. A good approach to face this aspect is to develop a machine learning based real time framework to analyze the signal and detect the faults. The last aim of this work is to present a preliminary study of data acquisition as a starting point to develop a real time framework to be built in the future. This work has been carried out using a SiPM sensor (which competes with the PMTs) with a fast ADC digitizer in real time

BICEP2 II: Experiment and Three-Year Data Set

We report on the design and performance of the BICEP2 instrument and on its three-year data set. BICEP2 was designed to measure the polarization of the cosmic microwave background (CMB) on angular scales of 1 to 5 degrees ($\ell$=40-200), near the expected peak of the B-mode polarization signature of primordial gravitational waves from cosmic inflation. Measuring B-modes requires dramatic improvements in sensitivity combined with exquisite control of systematics. The BICEP2 telescope observed from the South Pole with a 26~cm aperture and cold, on-axis, refractive optics. BICEP2 also adopted a new detector design in which beam-defining slot antenna arrays couple to transition-edge sensor (TES) bolometers, all fabricated on a common substrate. The antenna-coupled TES detectors supported scalable fabrication and multiplexed readout that allowed BICEP2 to achieve a high detector count of 500 bolometers at 150 GHz, giving unprecedented sensitivity to B-modes at degree angular scales. After optimization of detector and readout parameters, BICEP2 achieved an instrument noise-equivalent temperature of 15.8 $\mu$K sqrt(s). The full data set reached Stokes Q and U map depths of 87.2 nK in square-degree pixels (5.2 $\mu$K arcmin) over an effective area of 384 square degrees within a 1000 square degree field. These are the deepest CMB polarization maps at degree angular scales to date. The power spectrum analysis presented in a companion paper has resulted in a significant detection of B-mode polarization at degree scales.Comment: 30 pages, 24 figure

Sensors Fault Diagnosis Trends and Applications

Fault diagnosis has always been a concern for industry. In general, diagnosis in complex systems requires the acquisition of information from sensors and the processing and extracting of required features for the classification or identification of faults. Therefore, fault diagnosis of sensors is clearly important as faulty information from a sensor may lead to misleading conclusions about the whole system. As engineering systems grow in size and complexity, it becomes more and more important to diagnose faulty behavior before it can lead to total failure. In the light of above issues, this book is dedicated to trends and applications in modern-sensor fault diagnosis

EXPERIMENTAL ANALYSIS OF GATE DRIVE CONTROL SYSTEM FOR SYNCHRONOUS DC/DC CONVERTER

The design of the PCB board is important as it affects the overall performance of the overall system. The most common problem that affects the performance and efficiency of the PCB board are partitioning of the circuits, the problem of interconnecting traces, grounding schemes and thermal management. Overall, the primary objectives of the project are to understand the process flow of PCB and to acquire knowledge about PCB fabrication. Meanwhile, the secondary objectives of the project are to apply high frequency DC-DC Converter on PCB fabrication and lastly to test and verify the output of PCB fabrication. SRBC-PWM and SRBC-compensator-AGD are successfully implemented on PCB board. The knowledge about PCB design is acquired and the problems overcome while fabricating PCB are managed to overcome

Remote Attacks on FPGA Hardware

Immer mehr Computersysteme sind weltweit miteinander verbunden und über das Internet zugänglich, was auch die Sicherheitsanforderungen an diese erhöht. Eine neuere Technologie, die zunehmend als Rechenbeschleuniger sowohl für eingebettete Systeme als auch in der Cloud verwendet wird, sind Field-Programmable Gate Arrays (FPGAs). Sie sind sehr flexible Mikrochips, die per Software konfiguriert und programmiert werden können, um beliebige digitale Schaltungen zu implementieren. Wie auch andere integrierte Schaltkreise basieren FPGAs auf modernen Halbleitertechnologien, die von Fertigungstoleranzen und verschiedenen Laufzeitschwankungen betroffen sind. Es ist bereits bekannt, dass diese Variationen die Zuverlässigkeit eines Systems beeinflussen, aber ihre Auswirkungen auf die Sicherheit wurden nicht umfassend untersucht. Diese Doktorarbeit befasst sich mit einem Querschnitt dieser Themen: Sicherheitsprobleme die dadurch entstehen wenn FPGAs von mehreren Benutzern benutzt werden, oder über das Internet zugänglich sind, in Kombination mit physikalischen Schwankungen in modernen Halbleitertechnologien. Der erste Beitrag in dieser Arbeit identifiziert transiente Spannungsschwankungen als eine der stärksten Auswirkungen auf die FPGA-Leistung und analysiert experimentell wie sich verschiedene Arbeitslasten des FPGAs darauf auswirken. In der restlichen Arbeit werden dann die Auswirkungen dieser Spannungsschwankungen auf die Sicherheit untersucht. Die Arbeit zeigt, dass verschiedene Angriffe möglich sind, von denen früher angenommen wurde, dass sie physischen Zugriff auf den Chip und die Verwendung spezieller und teurer Test- und Messgeräte erfordern. Dies zeigt, dass bekannte Isolationsmaßnahmen innerhalb FPGAs von böswilligen Benutzern umgangen werden können, um andere Benutzer im selben FPGA oder sogar das gesamte System anzugreifen. Unter Verwendung von Schaltkreisen zur Beeinflussung der Spannung innerhalb eines FPGAs zeigt diese Arbeit aktive Angriffe, die Fehler (Faults) in anderen Teilen des Systems verursachen können. Auf diese Weise sind Denial-of-Service Angriffe möglich, als auch Fault-Angriffe um geheime Schlüsselinformationen aus dem System zu extrahieren. Darüber hinaus werden passive Angriffe gezeigt, die indirekt die Spannungsschwankungen auf dem Chip messen. Diese Messungen reichen aus, um geheime Schlüsselinformationen durch Power Analysis Seitenkanalangriffe zu extrahieren. In einer weiteren Eskalationsstufe können sich diese Angriffe auch auf andere Chips auswirken die an dasselbe Netzteil angeschlossen sind wie der FPGA. Um zu beweisen, dass vergleichbare Angriffe nicht nur innerhalb FPGAs möglich sind, wird gezeigt, dass auch kleine IoT-Geräte anfällig für Angriffe sind welche die gemeinsame Spannungsversorgung innerhalb eines Chips ausnutzen. Insgesamt zeigt diese Arbeit, dass grundlegende physikalische Variationen in integrierten Schaltkreisen die Sicherheit eines gesamten Systems untergraben können, selbst wenn der Angreifer keinen direkten Zugriff auf das Gerät hat. Für FPGAs in ihrer aktuellen Form müssen diese Probleme zuerst gelöst werden, bevor man sie mit mehreren Benutzern oder mit Zugriff von Drittanbietern sicher verwenden kann. In Veröffentlichungen die nicht Teil dieser Arbeit sind wurden bereits einige erste Gegenmaßnahmen untersucht