125,002 research outputs found

    Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS

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    The RD53 collaboration is currently designing a large scale prototype pixel readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC. The RD53A chip will be available by the end of the year 2017 and will be extensively tested to confirm if the circuit and the architecture make a solid foundation for the final pixel readout chips for the experiments at the HL-LHC. A test and data acquisition system for the RD53A chip is currently under development to perform single-chip and multi-chip module measurements. In addition, the verification of the RD53A design is performed in a dedicated simulation environment. The concept and the implementation of the test and data acquisition system and the simulation environment, which are based on a modular data acquisition and system testing framework, are presented in this work

    Phase Locked Loop Test Methodology

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    Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

    Deciding Disputes: Factors That Guide Chinese Courts in the Adjudication of Rural Responsibility Contract Disputes

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    Post-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Erik Larsson, Bart Vermeulen and Kees Goossens, A Distributed Architecture to Check Global Properties for Post-Silicon Debug, 2010, IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.</p

    Automating the IEEE std. 1500 compliance verification for embedded cores

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    The IEEE 1500 standard for embedded core testing proposes a very effective solution for testing modern system-on-chip (SoC). It proposes a flexible hardware test wrapper architecture, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Already several IP providers have announced compliance in both existing and future design blocks. In this paper we address the challenge of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE std. 1500. This is a mandatory step to fully trust the wrapper functionalities in applying the test sequences to the core. The proposed solution aims at implementing a verification framework allowing core providers and/or integrators to automatically verify the compliancy of their products (sold or purchased) to the standar

    IEEE Standard 1500 Compliance Verification for Embedded Cores

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    Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar

    Modular Scan Test for SoC Design

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    In this paper we try to reconfigure the existing scan system to a Modular Scan (MS) in order to adapt itself for future complexities of the chip design. One specific application of MS is the Multiprocessor System-on-Chip (MPSoC) design, where each core can have its own scan chain and also have concurrent testing procedure. MS is a process of arranging the scan chains flexibly for multiple usages during scan test. MS can be used in large chip designs to reduce the length of scan chains, and to reduce the testing time. MS based tests allow the test engineer to easily reconstruct the scan chain in an MPSoC design, if any of the existing cores needs to be replaced with a new core in order to meet the new set of specifications. To achieve such a type of testing, generic scan chain architecture needs to be developed in order to ensure an easy plug-n-play scan chain in the system architecture

    Modular Scan Test for SoC Design

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    In this paper we try to reconfigure the existing scan system to a Modular Scan (MS) in order to adapt itself for future complexities of the chip design. One specific application of MS is the Multiprocessor System-on-Chip (MPSoC) design, where each core can have its own scan chain and also have concurrent testing procedure. MS is a process of arranging the scan chains flexibly for multiple usages during scan test. MS can be used in large chip designs to reduce the length of scan chains, and to reduce the testing time. MS based tests allow the test engineer to easily reconstruct the scan chain in an MPSoC design, if any of the existing cores needs to be replaced with a new core in order to meet the new set of specifications. To achieve such a type of testing, generic scan chain architecture needs to be developed in order to ensure an easy plug-n-play scan chain in the system architecture

    A 6 mW, 5,000-Word Real-Time Speech Recognizer Using WFST Models

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    We describe an IC that provides a local speech recognition capability for a variety of electronic devices. We start with a generic speech decoder architecture that is programmable with industry-standard WFST and GMM speech models. Algorithm and architectural enhancements are incorporated in order to achieve real-time performance amid system-level constraints on internal memory size and external memory bandwidth. A 2.5 × 2.5 mm test chip implementing this architecture was fabricated using a 65 nm process. The chip performs a 5,000 word recognition task in real-time with 13.0% word error rate, 6.0 mW core power consumption, and a search efficiency of approximately 16 nJ per hypothesis.Quanta Computer (Firm)Irwin Mark Jacobs and Joan Klein Jacobs Presidential Fellowshi
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