A Note on “A Systematic (12,8) Code for Correcting Single Errors and Detecting Adjacent Errors”

J.W. Schwartz and J.K. Wolf (ibid., vol. 39, no. 11, pp. 1403-1404, Nov. 1990) gave a parity check matrix for a systematic (12,8) binary code that corrects all single errors and detects eight of the nine double adjacent errors within any of the three 4-bit nibbles. We present a parity check matrix for a systematic (12,8) binary code that corrects all single errors and detects any pair of errors within a nibble

Error control for reliable digital data transmission and storage systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code

Synthesis for circuit reliability

textElectrical and Computer Engineerin

Book Review

A Scholarly Review of “Error Control for Network-On-Chip Links” (Authors: Bo Fu and Paul Ampadu, 2012)Fu, B.; and Ampadu, P. 2012. Error Control for Network-On-Chip Links.Springer Science+Business Media, LLC, New York, NY, USA.Available: <http://dx.doi.org/10.1007/978-1-4419-9313-7>

Scheme for constructing graphs associated with stabilizer quantum codes

We propose a systematic scheme for the construction of graphs associated with binary stabilizer codes. The scheme is characterized by three main steps: first, the stabilizer code is realized as a codeword-stabilized (CWS) quantum code; second, the canonical form of the CWS code is uncovered; third, the input vertices are attached to the graphs. To check the effectiveness of the scheme, we discuss several graphical constructions of various useful stabilizer codes characterized by single and multi-qubit encoding operators. In particular, the error-correcting capabilities of such quantum codes are verified in graph-theoretic terms as originally advocated by Schlingemann and Werner. Finally, possible generalizations of our scheme for the graphical construction of both (stabilizer and nonadditive) nonbinary and continuous-variable quantum codes are briefly addressed.Comment: 42 pages, 12 figure

Codes for protection from synchronization loss and additive errors

Codes for protection from synchronization loss and additive error