A balanced Memristor-CMOS ternary logic family and its application

The design of balanced ternary digital logic circuits based on memristors and conventional CMOS devices is proposed. First, balanced ternary minimum gate TMIN, maximum gate TMAX and ternary inverters are systematically designed and verified by simulation, and then logic circuits such as ternary encoders, decoders and multiplexers are designed on this basis. Two different schemes are then used to realize the design of functional combinational logic circuits such as a balanced ternary half adder, multiplier, and numerical comparator. Finally, we report a series of comparisons and analyses of the two design schemes, which provide a reference for subsequent research and development of three-valued logic circuits.Comment: 15 pages, 30 figure

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic

University of Windsor Undergraduate Calendar 2001-2002

https://scholar.uwindsor.ca/universitywindsorundergraduatecalendars/1009/thumbnail.jp

Multiple-valued logic: technology and circuit implementation

Title from PDF of title page, viewed March 1, 2023Dissertation advisors: Masud H. Chowdhury and Yugyung LeeVitaIncludes bibliographical references (pages 91-107)Dissertation (Ph.D.)--Department of Computer Science and Electrical Engineering. University of Missouri--Kansas City, 2021Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore's law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. During this project, different technologies for Multiple-Valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies and (ii) availability of effective synthesis techniques. The main part of this project can be divided into two categories: (i) proposing different novel and efficient design for various logic and arithmetic circuits such as inverter, NAND, NOR, adder, multiplexer etc. (ii) proposing different fast and efficient design for various sequential and memory circuits. For the operation of the device, two of the very promising emerging technologies are used: Graphene Nanoribbon Field Effect Transistor (GNRFET) and Carbon Nano Tube Field Effect Transistor (CNTFET). A comparative analysis of the proposed designs and several state-of-the-art designs are also given in all the cases in terms of delay, total power, and power-delay-product (PDP). The simulation and analysis are performed using the H-SPICE tool with a GNRFET model available on the Nanohub website and CNTFET model available from Standford University website.Introduction -- Fundamentals and scope of multiple valued logic -- Technological aspect of multiple valued logic circuit -- Ternary logic gates using Graphene Nano Ribbon Field Effect Transistor (GNRFET) -- Ternary arithmetic circuits using Graphene Nano Ribbon Field Effect Transistor (GNRFET) -- Ternary sequential circuits using Graphene Nano Ribbon Field Effect Transistor (GNRFET) -- Ternary memory circuits using Carbon Nano Tube Field Effect Transistor (CNTFET) -- Conclusions & future wor

University of Windsor Undergraduate Calendar 2000-2001

https://scholar.uwindsor.ca/universitywindsorundergraduatecalendars/1008/thumbnail.jp

Reliability Abstracts and Technical Reviews January - December 1970

Reliability Abstracts and Technical Reviews is an abstract and critical analysis service covering published and report literature on reliability. The service is designed to provide information on theory and practice of reliability as applied to aerospace and an objective appraisal of the quality, significance, and applicability of the literature abstracted

Low-Complexity Soft-Decision Detection for Combating DFE Burst Errors in IM/DD Links

The deployment of non-binary pulse amplitude modulation (PAM) and soft decision (SD)-forward error correction (FEC) in future intensity-modulation (IM)/direct-detection (DD) links is inevitable. However, high-speed IM/DD links suffer from inter-symbol interference (ISI) due to bandwidth-limited hardware. Traditional approaches to mitigate the effects of ISI are filters and trellis-based algorithms targeting symbol-wise maximum a posteriori (MAP) detection. The former approach includes decision-feedback equalizer (DFE), and the latter includes Max-Log-MAP (MLM) and soft-output Viterbi algorithm (SOVA). Although DFE is easy to implement, it introduces error propagation. Such burst errors distort the log-likelihood ratios (LLRs) required by SD-FEC, causing performance degradation. On the other hand, MLM and SOVA provide near-optimum performance, but their complexity is very high for high-order PAM. In this paper, we consider a one-tap partial response channel model, which is relevant for high-speed IM/DD links. We propose to combine DFE with either MLM or SOVA in a low-complexity architecture. The key idea is to allow MLM or SOVA to detect only 3 typical DFE symbol errors, and use the detected error information to generate LLRs in a modified demapper. The proposed structure enables a tradeoff between complexity and performance: (i) the complexity of MLM or SOVA is reduced and (ii) the decoding penalty due to error propagation is mitigated. Compared to SOVA detection, the proposed scheme can achieve a significant complexity reduction of up to 94% for PAM-8 transmission. Simulation and experimental results show that the resulting SNR loss is roughly 0.3 to 0.4 dB for PAM-4, and becomes marginal 0.18 dB for PAM-8.Comment: This manuscript has been submitted to JL

Space Communications: Theory and Applications. Volume 3: Information Processing and Advanced Techniques. A Bibliography, 1958 - 1963

Annotated bibliography on information processing and advanced communication techniques - theory and applications of space communication

Undergraduate and Graduate Course Descriptions, 2023 Spring

Wright State University undergraduate and graduate course descriptions from Spring 2023