11 research outputs found

    Low-Power Wireless Distributed SIMD Architecture Concept: An 8051 Based Remote Execution Unit

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    Power has become a critical aspect in the design of modern wireless systems, especially in passive device nodes such as Radio Frequency Identification (RFID) tags, sensor nodes etc. Passive RFID tags in particular use simple logic that is used to respond with a unique code or data to identify objects when queried by an interrogator, whereas wireless passive sensor devices use microcontrollers for sensor data processing. There is a need for a Minimal Instruction Set Architecture (MISA) for such passive nodes with regard to low power. In this context, passive node capabilities need to be explored, possibly to suit target applications, in order to enable more than just identification and perhaps less than those of a conventional microcontroller Instruction Set Architecture (ISA). This dissertation research demonstrates a low-power wireless distributed processor architecture concept. The data and program instructions are stored on a powered interrogator providing wireless supervisory control for the remote passive node that has a basic processing core called the remote execution unit (REU). The interrogator and the passive node (REU) combination can be viewed as a complete processor or as multiple processing units forming the basis for a wireless distributed Single Instruction Multiple Data (SIMD) processor. This research introduces and investigates the REU architecture using an 8051-MISA with the goal of reducing power consumption of the system. A novel low power data-driven symbol decoder-CRC along with the 8051-MISA based execution core design form the frontend and core part of the REU architecture. Clocked and asynchronous digital logic implementations of the REU core design are presented and correspondingly the power, area and speed comparisons are also provided. Lack of strong support by commercial CAD tools is a major hurdle for synthesis of asynchronous designs. This research also presents a high-level design flow used to implement the asynchronous logic for the REU using traditional clocked CAD flows. This research work demonstrates immense potential to realize low power wireless passive sensor nodes for biomedical, automation, environmental, etc., applications especially while providing the basis for a programmable passive remote unit for distributed processing

    Energy autonomous systems : future trends in devices, technology, and systems

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    The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

    Adiabatic Approach for Low-Power Passive Near Field Communication Systems

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    This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches

    Energy processing circuits for low-power applications

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 199-205).Portable electronics have fueled the rich emergence of new applications including multi-media handsets, ubiquitous smart sensors and actuators, and wearable or implantable biomedical devices. New ultra-low power circuit techniques are constantly being proposed to further improve the energy efficiency of electronic circuits. A critical part of these energy conscious systems are the energy processing and power delivery circuits that interface with the energy sources and provide conditioned voltage and current levels to the load circuits. These energy processing circuits must maintain high efficiency and reduce component count for the final solution to be attractive from an energy, size and cost perspective. The first part of this work focuses on the development of on-chip voltage scalable switched capacitor DC-DC converters in digital CMOS processes. The converters are designed to deliver regulated scalable load voltages from 0.3V up to the battery voltage of 1.2V for ultra-dynamic voltage scaled systems. The efficiency limiting mechanisms of these on-chip DC-DC converters are analyzed and digital circuit techniques are proposed to tackle these losses. Measurement results from 3 test-chips implemented in 0.18pm and 65nm CMOS processes will be provided. The converters are able to maintain >75% efficiency over a wide range of load voltage and power levels while delivering load currents up to 8mA. An embedded switched capacitor DC-DC converter that acts as the power delivery unit in a 65nm subthreshold microcontroller system will be described. The remainder of the thesis deals with energy management circuits for battery-less systems. Harvesting ambient vibrational, light or thermal energy holds much promise in realizing the goal of a self-powered system. The second part of the thesis identifies problems with commonly used interface circuits for piezoelectric vibration energy harvesters and proposes a rectifier design that gives more than 4X improvement in output power extracted from the piezoelectric energy harvester. The rectifier designs are demonstrated with the help of a test-chip built in a 0.35pm CMOS process. The inductor used within the rectifier is shared efficiently with a multitude of DC-DC converters in the energy harvesting chip leading to a compact, cost-efficient solution. The DC-DC converters designed as part of a complete power management solution achieve efficiencies of greater than 85% even in the micro-watt power levels output by the harvester. The final part of the thesis deals with thermal energy harvesters to extract electrical power from body heat. Thermal harvesters in body-worn applications output ultra-low voltages of the order of 10's of milli-volts. This presents extreme challenges to CMOS circuits that are powered by the harvester. The final part of the thesis presents a new startup technique that allows CMOS circuits to interface directly with and extract power out of thermoelectric generators without the need for an external battery, clock or reference generators. The mechanically assisted startup circuit is demonstrated with the help of a test-chip built in a 0.35pm CMOS process and can work from as low as 35mV. This enables load circuits like processors and radios to operate directly of the thermoelectric generator without the aid of a battery. A complete power management solution is provided that can extract electrical power efficiently from the harvester independent of the input voltage conditions. With the help of closed-loop control techniques, the energy processing circuit is able to maintain efficiency over a wide range of load voltage and process variations.by Yogesh Kumar Ramadass.Ph.D

    Design and implementation of a multi-modal sensor with on-chip security

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    With the advancement of technology, wearable devices for fitness tracking, patient monitoring, diagnosis, and disease prevention are finding ways to be woven into modern world reality. CMOS sensors are known to be compact, with low power consumption, making them an inseparable part of wireless medical applications and Internet of Things (IoT). Digital/semi-digital output, by the translation of transmitting data into the frequency domain, takes advantages of both the analog and digital world. However, one of the most critical measures of communication, security, is ignored and not considered for fabrication of an integrated chip. With the advancement of Moore\u27s law and the possibility of having a higher number of transistors and more complex circuits, the feasibility of having on-chip security measures is drawing more attention. One of the fundamental means of secure communication is real-time encryption. Encryption/ciphering occurs when we encode a signal or data, and prevents unauthorized parties from reading or understanding this information. Encryption is the process of transmitting sensitive data securely and with privacy. This measure of security is essential since in biomedical devices, the attacker/hacker can endanger users of IoT or wearable sensors (e.g. attacks at implanted biosensors can cause fatal harm to the user). This work develops 1) A low power and compact multi-modal sensor that can measure temperature and impedance with a quasi-digital output and 2) a low power on-chip signal cipher for real-time data transfer

    Low Power Circuit Design in Sustainable Self Powered Systems for IoT Applications

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    The Internet-of-Things (IoT) network is being vigorously pushed forward from many fronts in diverse research communities. Many problems are still there to be solved, and challenges are found among its many levels of abstraction. In this thesis we give an overview of recent developments in circuit design for ultra-low power transceivers and energy harvesting management units for the IoT. The first part of the dissertation conducts a study of energy harvesting interfaces and optimizing power extraction, followed by power management for energy storage and supply regulation. we give an overview of the recent developments in circuit design for ultra-low power management units, focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. Three projects are presented in this area to reach a solution that provides reliable continuous operation for IoT sensor nodes in the presence of one or more natural energy sources to harvest from. The second part focuses on wireless transmission, To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner power amplifier, the Tx showed a measured energy efficiency of 0.2 nJ=bit and a normalized energy efficiency of 3.1 nJ=bit:mW when operating at output power levels up to -10 dBm and data rates of 3 Mbps

    Collective analog bioelectronic computation

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    Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D

    Energy Efficiency in Communications and Networks

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    The topic of "Energy Efficiency in Communications and Networks" attracts growing attention due to economical and environmental reasons. The amount of power consumed by information and communication technologies (ICT) is rapidly increasing, as well as the energy bill of service providers. According to a number of studies, ICT alone is responsible for a percentage which varies from 2% to 10% of the world power consumption. Thus, driving rising cost and sustainability concerns about the energy footprint of the IT infrastructure. Energy-efficiency is an aspect that until recently was only considered for battery driven devices. Today we see energy-efficiency becoming a pervasive issue that will need to be considered in all technology areas from device technology to systems management. This book is seeking to provide a compilation of novel research contributions on hardware design, architectures, protocols and algorithms that will improve the energy efficiency of communication devices and networks and lead to a more energy proportional technology infrastructure

    A Subthreshold Baseband Processor Core Design With Custom Modules and Cells for Passive RFID Tags

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