Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Integrated Circuit Design in US High-Energy Physics

This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future

CMOS SPAD-based image sensor for single photon counting and time of flight imaging

The facility to capture the arrival of a single photon, is the fundamental limit to the detection of quantised electromagnetic radiation. An image sensor capable of capturing a picture with this ultimate optical and temporal precision is the pinnacle of photo-sensing. The creation of high spatial resolution, single photon sensitive, and time-resolved image sensors in complementary metal oxide semiconductor (CMOS) technology offers numerous benefits in a wide field of applications. These CMOS devices will be suitable to replace high sensitivity charge-coupled device (CCD) technology (electron-multiplied or electron bombarded) with significantly lower cost and comparable performance in low light or high speed scenarios. For example, with temporal resolution in the order of nano and picoseconds, detailed three-dimensional (3D) pictures can be formed by measuring the time of flight (TOF) of a light pulse. High frame rate imaging of single photons can yield new capabilities in super-resolution microscopy. Also, the imaging of quantum effects such as the entanglement of photons may be realised. The goal of this research project is the development of such an image sensor by exploiting single photon avalanche diodes (SPAD) in advanced imaging-specific 130nm front side illuminated (FSI) CMOS technology. SPADs have three key combined advantages over other imaging technologies: single photon sensitivity, picosecond temporal resolution and the facility to be integrated in standard CMOS technology. Analogue techniques are employed to create an efficient and compact imager that is scalable to mega-pixel arrays. A SPAD-based image sensor is described with 320 by 240 pixels at a pitch of 8μm and an optical efficiency or fill-factor of 26.8%. Each pixel comprises a SPAD with a hybrid analogue counting and memory circuit that makes novel use of a low-power charge transfer amplifier. Global shutter single photon counting images are captured. These exhibit photon shot noise limited statistics with unprecedented low input-referred noise at an equivalent of 0.06 electrons. The CMOS image sensor (CIS) trends of shrinking pixels, increasing array sizes, decreasing read noise, fast readout and oversampled image formation are projected towards the formation of binary single photon imagers or quanta image sensors (QIS). In a binary digital image capture mode, the image sensor offers a look-ahead to the properties and performance of future QISs with 20,000 binary frames per second readout with a bit error rate of 1.7 x 10-3. The bit density, or cumulative binary intensity, against exposure performance of this image sensor is in the shape of the famous Hurter and Driffield densitometry curves of photographic film. Oversampled time-gated binary image capture is demonstrated, capturing 3D TOF images with 3.8cm precision in a 60cm range

A SPAD-Based QVGA Image Sensor for Single-Photon Counting and Quanta Imaging

A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8-μm pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e- minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with 4.6× overexposure latitude and 0.168e- read noise

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems

We present Swallow, a scalable many-core architecture, with a current configuration of 480 x 32-bit processors. Swallow is an open-source architecture, designed from the ground up to deliver scalable increases in usable computational power to allow experimentation with many-core applications and the operating systems that support them. Scalability is enabled by the creation of a tile-able system with a low-latency interconnect, featuring an attractive communication-to-computation ratio and the use of a distributed memory configuration. We analyse the energy and computational and communication performances of Swallow. The system provides 240GIPS with each core consuming 71--193mW, dependent on workload. Power consumption per instruction is lower than almost all systems of comparable scale. We also show how the use of a distributed operating system (nOS) allows the easy creation of scalable software to exploit Swallow's potential. Finally, we show two use case studies: modelling neurons and the overlay of shared memory on a distributed memory system.Comment: An open source release of the Swallow system design and code will follow and references to these will be added at a later dat

Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Array

Since they were introduced, floating-gate (FG) transistors have been used as non-volatile digital memory. Recent research has shown that floating-gate transistors can be successfully used as analog memory, specifically as programmable voltage and current sources. However, their proliferation has been limited due to the complex programming procedure and the complex testing equipment. Analog applications such as field-programmable analog arrays (FPAAs) require hundreds to thousands of floating-gate transistors on a single chip which makes the programming process even more complicated and very challenging. Therefore, a simplified, compact, and low-power scheme to program FGs are necessary. This work presents an improved version of the typical methodology for FG programming. Additionally, a novel programming methodology that utilizes negative voltages is presented here. This method simplifies the programming process by eliminating the use of supplementary and complicated infrastructure circuits, which makes the FG transistor a good candidate for low-power wireless sensor nodes and portable systems

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed

Nanoscale Nonvolatile Memory Circuit Design using Emerging Spin Transfer Torque Magnetic Random Access Memory

Title from PDF of title page, viewed August 25, 2017Thesis advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 67-71)Thesis (M.S.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016The spin transfer torque magnetic random access memory (STT-MRAM) is suitable for embedded and second level cache memories in the mobile CPUs. STT-MRAM is a highly potential nonvolatile memory (NVM) technology. There has been a growing demand to improve the efficiency and reliability of the NVM circuits and architectures. we present a modified STT MRAM cell design, where each cell is comprised of one magnetic tunneling junction (MTJ) device and a regular access transistor. We provide analysis of device, circuit and memory architecture level issues of STT-MRAM. The Modified 1M1T STT-MRAM bit cell circuit offers simpler and more area- and power- efficient design compared to the existing STT-MRAM cell design. Some device-circuit co-design issues are investigated to demonstrate ways to reduce delay in MRAM circuits based on MTJ. An 8x8 conventional MRAM array is implemented using the existing 2M2T cell and the Modified 1M1T cell to perform a comparative analysis at the architecture level. The non-volatile nature of the proposed STT-MRAM is verified through SPICE simulation. The circuit implementations and simulations are performed for 45nm technology node. As the transistor scales down it is prone to subthreshold leakage, gate-dielectric leakage, Short channel effect and drain induced barrier lowering. Now alternative of Access transistor is needed. We are using FinFET as access transistor in the STT-MRAM bit cell. FinFET based bit cell is designed to get an advantage of scaling down. Analysis is done and proven that the power consumption, standalone leakage current is less when compared to NMOS based STT-MRAM bit cell. Also determined FinFET based bit cell produces less access time to access the logic value from MTJ. Now, Industry is looking to have computational and storage capability together and that can be achieved through STT-MRAM. Addition to that there is a possibility to reduce power consumption and leakage more. So replacing FinFET technology with Carbon Nano Tube Field Effect Transistor (CNTFET) is required. As the conventional STT-MRAM requires certain current to reverse the magnetization of MTJ and one CNTFET alone cannot produce sufficient current required to store the logic value into MTJ. So new Bit cell is proposed using 3 CNTFET and 1 MTJ, this bit cell is capable of storing 3 logic values at a time that is capable of doing computation and act as AND gate. Also it utilizes less power to be in active region. Sensing of any memory system is one of the main challenge in industry to get better performance with less resources. Conventional Sense Amplifier (SA) used to sense the value from SRAM, DRAM memory system is also used to sense the STT-MRAM memory. But use of conventional SA is prone to some error. Modified Sense Amplifier is designed to overcome the error produced from the conventional SA. It is compared with all the existing SA to get the performance details of the modified SA.Introduction -- Planar NMOS based STT-MRAM bit cell analysis and circuit designing -- Performance improvement using FINFET based STT-MRAM circuit design -- Logic-in-memory using CNT-FET based STT-MRAM bit cell and optimization -- Error free sense amplifier design for STT-MRAM nonvolatile memor