InAs Nanowire Devices and Circuits

Since the introduction of the transistor and the integrated circuit, the semiconductor industry has developed at a remarkable pace. By continuously fabricating smaller and faster transistors, it has been possible to maintain an exponential increase in performance, a phenomenon famously described by Moore’s Law. Today, billions of transistors are integrated on a single chip and the size of a transistor is on the scale of tens of nanometres. Until recently, the improvements in performance and integration density have been mostly driven by scaling down the transistor size. However, as the length scale is rapidly approaching that of only a few atoms, this scaling paradigm may not continue forever. Instead, the research community, as well as the industry, is investigating alternative structures and materials in order to further increase the performance. One emerging technology for use in future electronic circuits is transistors based on nanowires. The nanowire transistor structure investigated in this work combines a number of key technologies to achieve a higher performance than traditional Si-based transistors. Epitaxially grown nanowires are naturally oriented in the vertical direction, which means that the devices may be fabricated from the bottom and up. This three-dimensional structure allows a higher integration density and enables the gate to completely surround the channel in a gate-all-around configuration. Combined with a high-k dielectric, this results in an excellent electrostatic gate control. Furthermore, nanowires have the unique ability to combine semiconductor materials with significantly different lattice constants. By introducing InAs as a channel material, a much higher electron mobility than for Si is achieved. In this work, simulations of nanowire-based devices are performed and the ultimate performance is predicted. A nanowire transistor architecture with a realistic footprint is proposed and a roadmap is established for the scaling of the device structure, based on a set of technology nodes. Benchmarking is performed against competing technologies, both from a device and circuit perspective. The physical properties of nanowire transistors, and the corresponding capacitor structure, are investigated by band-structure simulations. Based on these simulations, a ballistic transport model is used to derive the intrinsic transistor characteristics. This is combined with an extensive evaluation and optimization of the parasitic elements in the transistor structure for each technology node. It is demonstrated that an optimized nanowire transistor has the potential to operate at terahertz frequencies, while maintaining a low power consumption. A high quality factor and extremely high integration density is predicted for the nanowire capacitor structure. It is concluded that InAs nanowire devices show great potential for use in future electronic circuits, both in digital and analogue applications

High Electron Mobility Transistors: Performance Analysis, Research Trend and Applications

In recent years, high electron mobility transistors (HEMTs) have received extensive attention for their superior electron transport ensuring high speed and high power applications. HEMT devices are competing with and replacing traditional field‐effect transistors (FETs) with excellent performance at high frequency, improved power density and satisfactory efficiency. This chapter provides readers with an overview of the performance of some popular and mostly used HEMT devices. The chapter proceeds with different structures of HEMT followed by working principle with graphical illustrations. Device performance is discussed based on existing literature including both analytical and numerical models. Furthermore, some notable latest research works on HEMT devices have been brought into attention followed by prediction of future trends. Comprehensive knowledge of up‐to‐date results, future directions, and their analysis methodology would be helpful in designing novel HEMT devices

Investigation of advanced GaN HEMTs for digital and high frequency applications

The physical features of Gallium nitride (GaN) and the related materials make them very suitable for the fabrication of power semiconductor devices. The large band gap and high electrical breakdown field strength of GaN in combination with high-density two-dimensional electron gases induced by polarization in AlGaN/GaN interface enables the development of transistors with high off-state voltages, low on-state resistances and low switching charges. However the transistors made of conventional GaN HEMTs have already approached their performance limit. In order to meet the future needs of power semiconductor devices, research efforts are being put on nonclassical HEMT concepts e.g. superjunction GaN HEMTs, PNT GaN HEMTs and GaN MIS FETs or on using a new barrier materials such AlScN and AlYN. This work aims to push GaN technology by new approaches in design and characterization of highly-efficient GaN transistors in order to release its full potential. The aim of the present work is the evaluation of different nonclassical GaN HEMT concepts regarding their performance and suitability for logic, power-switching and RF ampflication applications and to define their design space. The investigations are based on numerical device simulations supported by analytical calculations. It is shown that the simple and robust drift-diffusion model is well suited for the simulation of such nonclassical devices. The co-existence of two dimensional- electron and hole gases in GaN-based heterostructures is investigated by means of analytical models, developed in the frame of this work, and self-consistent numerical solutions of the Schrödinger and Poisson equations. It is shown that for certain combinations of bias conditions and layer design coexisting 2DEGs and 2DHGs can be formed in GaN/AlGaN/GaN structures, where the 2DHG is located at the cap/barrier interface and the 2DEG resides at the barrier/bulk interface. Once a 2DHG is created, the effect of the gate voltage on the 2DEG diminishes rapidly and a saturation of the 2DEG density is observed. Furthermore, in structures with thin barriers it is much more difficult to create a 2DHG even for large surface potentials. The formation of second channel in AlGaN/GaN/AlGaN/GaN heterostructures has been investigated. It has been shown that for certain combinations of bias conditions and layer design coexisting two channels can be formed in AlGaN2/GaN2/AlGaN1/GaN1 structures where both channels are located at the AlGaN1/GaN1 and AlGaN2/GaN2. Once a second channel is created, the effect of the gate voltage on the first 2DEG diminishes rapidly and a saturation of the drain current is observed. Special attention was paid to a novel vertical inverter design by employing these two channels. On the other hand, theoretical investigations of AlGaN/GaN HEMT structures for power switch applications focus on the estimation of oxide interface charges in MIS HEMT structures and on two simulation studies dealing with alternative normally-off HEMT concepts. The study on oxide interface charges is based on a comparison of measured and simulated threshold voltages of HEMTs with and without an oxide layer underneath the gate. Moreover, we developed a simple analytical threshold voltage model for the MIS HEMT structure which can be used to estimate the interface charge with a pocket calculator. We propose also a new approach to combine the effect of a p-type doped cap layer with that of a gate oxide for designing and achieving normally-off HEMT. We focus on the structures proposed by Ota et al. using 1D Schrödinger-Poisson simulations and analytical models. In particular, our analytical model shows that the threshold voltage is independent on the thicknesses of both the PNT layer and the strained GaN channel layer. Additionally, we discuss options to increase the electron sheet density in the ungated regions in order to reduce the source/drain resistances. Moreover, gated cubic InGaN/InN heterostructures for application in InN-based HEMTs are investigated theoretically. The formation of two-dimensional carrier gases in InGaN/InN structures is studied in detail and design issues for the InGaN barrier are investigated. It is shown that for certain surface potentials an undesirable saturation of the sheet density of the electron gas in the InN channel layer may occur. Options to enhance the electron sheet density in the channel and surface potential ranges for proper transistor operation are presented. Finally, the formation of two-dimensional electron gases in lattice-matched AlScN/GaN and AlYN/GaN heterostructures is investigated by numerical self-consistent solutions of the Schrödinger and Poisson equations. The electron concentration profiles and the resulting 2DEG sheet densities in these heterostructures are calculated and compared to those occurring at AlGaN/GaN interfaces. The combined effect of the strong polarization-induced bound charges and the large conduction band offsets at the AlScN/GaN and AlYN/GaN heterojunctions results in the formation of 2DEGs with very high electron sheet densities.about 4 … 5 times as large as those in Al0.3Ga0.7N/GaN. Our results demonstrate the potential of AlScN and AlYN barriers for GaN-based high electron mobility transistors.Die physikalischen Eigenschaften des Galliumnitrid (GaN) und der darauf basierenden Materialien eignen sich besonders zur Herstellung von leistungselektronischen Bauelementen. Die große Bandlücke und hohe elektrische Durchbruchfeldstärke von GaN in Kombination mit einem zweidimensionalen Elektronengas hoher Dichte durch induzierte Polarisation in der AlGaN/GaN-Grenzfläche ermöglicht die Entwicklung von Transistoren mit hohen Sperrspannungen, niedrigen Durchlasswiderständen und niedrigen Schaltladungen. Die aus herkömmlichen GaN-HEMTs hergestellten Transistoren haben jedoch bereits ihre Leistungsgrenze erreicht. Um die zukünftigen Bedürfnisse von leistungselektronischen Bauelementen zu erfüllen, werden Forschungen zu nichtklassischen HEMT-Konzepten, zum Beispiel Superjunction GaN-HEMT, PNT GaN-HEMTs oder zu neuartigen Barrierematerialien durchgeführt. Diese Arbeit will die GaN-Technologie durch neue Ansätze in Design und Charakterisierung hocheffizienter GaN-Transistoren vorantreiben, um ihr volles Potential zu entfalten. Das Ziel der vorliegenden Arbeit ist es, verschiedene nichtklassische GaN HEMT-Konzepte hinsichtlich ihrer Performance sowie ihrer Eignung für zukünftige Logik, leistungselektronisch und RF Anwendungen zu bewerten und ihren Designspielraum einzugrenzen. Die Untersuchungen basieren auf numerischen Bauelementesimulationen unter Zuhilfenahme analytischer Berechnungen. Es wird gezeigt, dass das einfache und robuste Drift-Diffusionsmodell für die Simulation solcher nichtklassischen Bauelemente geeignet ist. Die Koexistenz von zweidimensionalen Elektronen- und Löchergasen in GaN-basierten Heterostrukturen wird mittels analytischer Modelle, die im Rahmen dieser Arbeit entwickelt wurden, und selbstkonsistenten numerischen Lösungen der Schrödinger- und Poisson-Gleichungen untersucht. Es kann gezeigt werden, dass für bestimmte Kombinationen von Bias-Bedingungen und Schichtdesign koexistierende 2DEGs und 2DHGs in GaN/AlGaN/GaN-Strukturen gebildet werden können, wobei sich das 2DHG an der Grenzfläche zwischen Grenzfläche und Grenzfläche befindet. Sobald ein 2DHG erzeugt ist, nimmt der Effekt der Gate-Spannung auf das 2DEG schnell ab und eine Sättigung der 2DEG-Dichte wird beobachtet. Außerdem ist es in Strukturen mit dünnen Barrieren viel schwieriger, ein 2DHG selbst für große Oberflächenpotentiale zu erzeugen. Die Formierung eines zweiten Kanals in AlGaN/GaN/AlGaN/GaN Heterostrukturen wurde untersucht. Es wurde gezeigt, dass für bestimmte Kombinationen von Bias-Bedingungen und Schichtdesign koexistierende zwei Kanäle in AlGaN2/GaN2/AlGaN1/GaN1-Strukturen gebildet werden können, wobei sich beide Kanäle am AlGaN1/GaN1 und AlGaN2/GaN2 befinden. Sobald der zweite Kanal erzeugt ist, nimmt die Wirkung der Gate-Spannung auf das erste 2DEG schnell ab und eine Sättigung des Drain-Stroms wird beobachtet. Besondere Aufmerksamkeit wurde auf einen neuartigen Inverter mit vertikalem Aufbauen gelegt, indem diese zwei Kanäle verwendet wurden. Andererseits konzentrieren sich theoretische Untersuchungen von AlGaN/GaN-HEMT-Strukturen für leistungselektronische Anwendungen auf die Abschätzung von Oxidgrenzflächenladungen in MIS-HEMT-Strukturen, und es werden zwei Simulationsstudien zu alternativen selbstsperrenden HEMT-Konzepten vorgestellt. Die Untersuchung von Oxidgrenzflächenladungen basiert auf einem Vergleich von gemessenen und simulierten Schwellenspannungen experimenteller HEMTs mit und ohne Al2O3-Schicht unter dem Gate. Wir finden, dass in beiden Fällen die geschätzte Oxidgrenzflächenladung die gleiche ist. Darüber hinaus entwickelten wir ein einfaches analytisches Schwellenspannungsmodell für die MIS HEMT Struktur, mit dem die Grenzflächenladung mit einem Taschenrechner abgeschätzt werden kann. Wir schlagen auch einen neuen Ansatz vor, bei dem die Wirkung einer p-dotierten Deckschicht mit der eines Gateoxids kombiniert wird, um einen selbstsperrenden HEMT zu erreichen. Wir konzentrieren uns auf die von Ota et al. mit 1D-Schrödinger-Poisson-Simulationen. Insbesondere zeigt unser analytisches Modell, dass die Schwellenspannung unabhängig von der Dicke sowohl der PNT-Schicht als auch der gespannten GaN-Kanalschicht ist. Darüber hinaus diskutieren wir Optionen zur Erhöhung der Elektronendichte in den ungesteuerten (ungated) Bauelementbereichen, um die Source/Drain-Widerstände zu reduzieren. Darüber hinaus werden gated kubische InGaN/InN-Heterostrukturen für die Anwendung in InN-basierten Transistoren mit hoher Elektronenmobilität theoretisch untersucht. Die Bildung zweidimensionaler Trägergase in InGaN/InN-Strukturen wird im Detail untersucht und Designprobleme für die InGaN-Barriere untersucht. Es wird gezeigt, dass für bestimmte Oberflächenpotentiale eine unerwünschte Sättigung der Schichtdichte des Elektronengases in der InN-Kanalschicht auftreten kann. Optionen zur Verbesserung der Elektronendichte in den Kanal- und Oberflächenpotentialbereichen für einen geeigneten Transistorbetrieb werden vorgestellt. Abschließend wird die Bildung zweidimensionaler Elektronengase (2DEGs) in gitterangepassten AlScN/GaN- und AlYN/GaN-Heterostrukturen durch numerische selbstkonsistente Lösungen der Schrödinger- und Poisson-Gleichungen untersucht. Die Elektronenkonzentrationsprofile und die resultierenden 2DEG-Schichtdichten in diesen Heterostrukturen werden berechnet und mit denen verglichen, die an AlGaN/GaN-Grenzflächen auftreten. Die kombinierte Wirkung der stark polarisationsinduzierten gebundenen Ladungen und der großen Leitungsbandoffsets an den AlScN/GaN- und AlYN/GaN-Heteroübergängen führt zur Bildung von 2DEGs mit sehr hohen Elektronendichtedichten. Für die AlScN/GaN- und AlYN/GaN-Heterostrukturen werden 2DEG-Schichtdichten von etwa 4 bis 5-mal so groß wie für Al0,3Ga0,7N/GaN-Strukturen berechnet. Unsere Ergebnisse demonstrieren das Potenzial von AlScN- und AlYN-Barrieren für GaN-basierte Transistoren mit hoher Elektronenmobilität

Fabrication and Physics-Based Modeling of Polar AlGaN/GaN and AlInGaN/GaN HFETs

Since their advent, polar AlGaN/GaN hetero-junction field effect transistors (HFETs) have drawn a great deal of attention especially in high frequency/high power applications. However, the superb prospects of these transistors are affected by a few drawbacks such as aging/crack formation under strain, presence of high gate-leakage, and challenging realization of enhancement-mode (normally-off) devices. Quite recently, study of quaternary AlInGaN barriers has been presented as a promising avenue for fulfilling various design demands including: lattice matching, polarization matching, and positive shifting the inherently negative threshold voltage of AlGaN/GaN HFETs. However, thus far only a limited scope of theoretical studies on AlInGaN/GaN hetero-structure characteristics has been reported. As part of this thesis, the two dimensional electron gas (2DEG) characteristics of gated metal-face wurtzite AlInGaN/GaN hetero-junctions as function of physical and compositional properties of the hetero-junction are theoretically evaluated using the variational method. According to this study, a considerable shift in the positive direction for the threshold voltage of AlInGaN/GaN HFETs can be achieved by engineering both the spontaneous and the piezoelectric polarization (using a quaternary AlInGaN barrier-layer of appropriate mole-fractions). Succeeding this study, a novel quaternary lattice-match layer structure based on employing a bilayer barrier for improving the carrier confinement in the channel of enhancement-mode AlInGaN/GaN HFETs is for the first time proposed. It is shown that while the proposed layer structure substantially improves the carrier confinement in the GaN channel layer, it also upholds the merits of employing a lattice-match barrier towards achieving an enhancement-mode operation. One of the most important device characteristics of AlGaN/GaN HFETs which is often poorly understood is the gate-leakage current. As part of this thesis, reverse gate-leakage of AlGaN/GaN HFETs is studied over a wide range of lattice-temperatures. While unveiling an obscure path for gate leakage through the mesa sidewall, a model considering different leakage paths, including the identified sidewall leakage, is presented. It is illustrated that the sidewall path to the 2DEG is associated with the Poole-Frenkel electron emission. The novel contribution of the present analysis is that it postulates that in absence of absolute uniformity, Fowler-Nordheim (FN) tunneling takes place through only a small portion of the surface of the barrier, which boasts the highest electric field or the smallest Schottky barrier height. This consideration, allows the model to avoid unrealistic values for quantities such as effective electron mass (that has plagued many of the existing models). Also as part of this thesis work, process recipe for microfabrication of submicron gate AlGaN/GaN HFETs using electron beam lithography was developed at McGill’s nano-tools micro-fabrication facilities. The results of DC characterization of the fabricated transistors along with the results of the DC stress test are presented

GaN heterojunction FET device Fabrication, Characterization and Modeling

This dissertation is focused on the research efforts to develop the growth, processing, and modeling technologies for GaN-based Heterojunction Field Effect Transistors (HFETs). The interest in investigating GaN HFETs is motivated by the advantageous material properties of nitride semiconductor such as large band gap, large breakdown voltage, and high saturation velocity, which make it very promising for the high power and microwave applications. Although enormous progress has been made on GaN transistors in the past decades, the technologies for nitride transistors are still not mature, especially concerning the reliability and stability of the device. In order to improve the device performance, we first optimized the growth and fabrication procedures for the conventional AlGaN barrier HFET, on which high carrier mobility and sheet density were achieved. Second, the AlInN barrier HFET was successfully processed, with which we obtained improved I-V characteristics compared with conventional structure. The lattice-matched AlInN barrier is beneficial in the removal of strain, which leads to better carrier transport characteristics. Furthermore, new device structures have been examined, including recess-gate HFET with n+ GaN cap layer and gate-on-insulator HFET, among which the insertion of gate dielectrics helps to leverage both DC and microwave performances. In order to depict the microwave behavior of the HFET, small signal modeling approaches were used to extract the extrinsic and intrinsic parameters of the device. An 18-element equivalent circuit model for GaN HFET has been proposed, from which various extraction methods have been tested. Combining the advantages from the cold-FET measurements and hot-FET optimizations, a hybrid extraction method has been developed, in which the parasitic capacitances were attained from the cold pinch-off measurements while the rest of the parameters from the optimization routine. Small simulation error can be achieved by this method over various bias conditions, demonstrating its capability for the circuit level design applications for GaN HFET. Device physics modeling, on the other hand, can help us to reveal the underlying physics for the device to operate. With the development of quantum drift-diffusion modeling, the self-consistent solution to the Schrödinger-Poisson equations and carrier transport equations were fulfilled. Lots of useful information such as band diagram, potential profile, and carrier distribution can be retrieved. The calculated results were validated with experiments, especially on the AlInN layer structures after considering the influence from the parasitic Ga-rich layer on top of the spacer. Two dimensional cross-section simulation shows that the peak of electrical field locates at the gate edge towards the drain, and of different kinds of structures the device with gate field-plate was found to efficiently reduce the possibility of breakdown failure

The development of silicon compatible processes for HEMT realisation

Compound semiconductor (III-V) devices are crucially important in a range of RF/microwave applications. High Electron Mobility Transistors (HEMTs), as the best low noise high frequency compound semiconductor devices, have been utilised in various applications at microwave and mm-wave frequencies such as communications, imaging, sensing and power. However, silicon based manufacturing will always be the heart of the semiconductor industry. III-V devices are conventionally fabricated using gold-based metallisation and lift off processes, which are incompatible with silicon manufacturing processes based on blanket metal or dielectric deposition and subtractive patterning by dry etching techniques. Therefore, the challenge is to develop silicon compatible processes for the realisation of compound semiconductor devices, whilst not compromising the device performance. In this work, silicon compatible processes for HEMT realisation have been developed, including the demonstration of a copper-based T-gate with the normalised DC resistance of 42 Ω/mm, and the presentation of a gate-first process flow which can incorporate the copper-based T-gate. The copper electroplating process for fabricating T-gate head with the maximum width of 2.5 µm, low damage inductively coupled plasma molybdenum etching process for realising T-gate foot with the minimum footprint of 30 nm, and the full gate-first process flow with non-annealed ohmic contact are described in detail. In addition, this thesis also describes the fabrication and characterisation of a 60 nm footprint gold-based T-gate HEMT realised by conventional III-V processes, yielding a cutoff frequency fT of 183GHz and maximum oscillation frequency fmax of 156GHz. In the comparison between these two types of HEMT, it is anticipated that a HEMT with the copper-based T-gate would not only have a larger maximum frequency of oscillation fmax, but also an easier incorporation into a silicon based manufacturing fab in terms of process technologies, than a HEMT with the gold-based T-gate

Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Advanced characterisation of novel III-nitride semiconductor based photonics and electronics on polar and non-polar substrates

Advanced characterisation has been carried out on a number of novel III-nitride based photonics and electronics, including micro-LED arrays achieved by a direct epitaxy approach, high performance c-plane HEMTs structure achieved by a novel growth method and non-polar GaN/AlGaN HEMTs. In this work, a systematic study has been conducted to understand the electrical properties of these novel devices, demonstrating their excellent properties. Furthermore, the electrical properties are directly related to epitaxial growth, which provides useful information for further improving device performance, such as 2D growth mode for GaN on a large lattice-mismatched substrate which plays an important in obtaining high breakdown and minimised leakage current for HEMTs. Micro-LEDs are the key elements for a microdisplay system, where electrical properties are extremely important. Potentially, any leakage current can trigger to turn on any neighbouring microLEDs which are supposed to be off. Instead of using conventional fabrication methods which normally enhances leakage current, our team developed a direct epitaxy approach to achieving microLED arrays. In this work, detailed I-V characteristic and capacitance measurements have been conducted on these novel microLED devices, demonstrating leakage currents as low as 14.1 nA per LED and a smooth negative capacitance curve instead of odd positive capacitance performances. Furthermore, a comparison study between our microLEDs and the microLEDs prepared using the conventional method indicates our device shows a large reduction of size-dependent inefficiency while such a behaviour is never observed on the microLEDs fabricated by the conventional methods. Unlike the classic two-step method for GaN growth on large lattice-matched sapphire, our team developed a high-temperature AlN buffer technology, where a 2D growth mode, instead of an initial 2D and then 3D growth mode that typically happens for the growth of conventional GaN growth, takes place through the whole growth process. This method allows us to achieve a breakdown electric field strength of 2.5 MV/cm, a leakage current of as low as 41.7 pA at 20 V and saturation current densities as high as 1.1 A/mm. In this work a systematic study has conducted in order to establish a relationship between the excellent device performance and material properties, where a very low screw dislocation density plays a critical role, while our 2D growth method can provide an excellent opportunity for achieving such a low screw dislocation density. This demonstrates the major advantage over the classic two-step method in the growth of power and RF devices. In our case, we have obtained an unintentional doping as low as 2×10^14 cm-3 and screw dislocation densities of 2.3×10^7 cm-2. Compared with c-plane GaN based HEMTs due to its intrinsic polarisation, non-polar GaN/AlGaN HEMTs on r-plane sapphire yields potential advantages in terms of the fabrication of normal-off devices which are particularly important for practical applications. However, it is a great challenge to achieve high quality non-polar GaN on sapphire. Some initial work has been conducted, where the detailed characterisation indicates an electron mobility of 43 cm2 V-1 s-1 has been initially obtained. Furthermore, instead of using an AlGaN/GaN heterostructure with a modulation doping, we deliberately use a quantum well structure as an electron channel, leading to a mobility of 76 cm2 V-1 s-1. Our simulations as well as measurements also provide a guideline for optimising the general epitaxial structure

Analysis of fluctuations in semiconductor devices

The random nature of ion implantation and diffusion processes as well as inevitable tolerances in fabrication result in random fluctuations of doping concentrations and oxide thickness in semiconductor devices. These fluctuations are especially pronounced in ultrasmall (nanoscale) semiconductor devices when the spatial scale of doping and oxide thickness variations become comparable with the geometric dimensions of devices. In the disseration, the effects of these fluctuations on device characteristics are analyzed by using a new technique for the analysis of random doping and oxide thickness induced fluctuations. This technique is universal in nature in the sense that it is applicable to any transport model (drift-diffusion, semiclassical transport, quantum transport etc.) and it can be naturally extended to take into account random fluctuations of the oxide (trapped) charges and channel length. The technique is based on linearization of the transport equations with respect to the fluctuating quantities. It is computationally much (a few orders of magnitude) more efficient than the traditional Monte-Carlo approach and it yields information on the sensitivity of fluctuations of parameters of interest (e.g. threshold voltage, small-signal parameters, cut-off frequencies, etc.) to the locations of doping and oxide thickness fluctuations. For this reason, it can be very instrumental in the design of fluctuation-resistant structures of semiconductor devices. Quantum mechanical effects are taken into account by using the density-gradient model as well as through self-consistent Poisson-Schrödinger computations. Special attention is paid to the presenting of the technique in a form that is suitable for implementation on commercial device simulators. The numerical implementation of the technique is discussed in detail and numerous computational results are presented and compared with those previously published in literature

DESIGN, SIMULATION AND FABRICATION OF ALGAN/GAN NORMALLY-OFF HIGH ELECTRON MOBILITY TRANSISTORS WITH INVESTIGATION ON TEMPERATURE STABILITY

Ph.DDOCTOR OF PHILOSOPH