Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices

The high demand for memory capacity in modern datacenters has led to multiple lines of innovation in memory expansion and disaggregation. One such effort is Compute eXpress Link (CXL)-based memory expansion, which has gained significant attention. To better leverage CXL memory, researchers have built several emulation and experimental platforms to study its behavior and characteristics. However, due to the lack of commercial hardware supporting CXL memory, the full picture of its capabilities may still be unclear to the community. In this work, we explore CXL memory's performance characterization on a state-of-the-art experimental platform. First, we study the basic performance characteristics of CXL memory using our proposed microbenchmark. Based on our observations and comparisons to standard DRAM connected to local and remote NUMA nodes, we also study the impact of CXL memory on end-to-end applications with different offloading and interleaving policies. Finally, we provide several guidelines for future programmers to realized the full potential of CXL memor

Separation logic for high-level synthesis

High-level synthesis (HLS) promises a significant shortening of the digital hardware design cycle by raising the abstraction level of the design entry to high-level languages such as C/C++. However, applications using dynamic, pointer-based data structures remain difficult to implement well, yet such constructs are widely used in software. Automated optimisations that leverage the memory bandwidth of dedicated hardware implementations by distributing the application data over separate on-chip memories and parallelise the implementation are often ineffective in the presence of dynamic data structures, due to the lack of an automated analysis that disambiguates pointer-based memory accesses. This thesis takes a step towards closing this gap. We explore recent advances in separation logic, a rigorous mathematical framework that enables formal reasoning about the memory access of heap-manipulating programs. We develop a static analysis that automatically splits heap-allocated data structures into provably disjoint regions. Our algorithm focuses on dynamic data structures accessed in loops and is accompanied by automated source-to-source transformations which enable loop parallelisation and physical memory partitioning by off-the-shelf HLS tools. We then extend the scope of our technique to pointer-based memory-intensive implementations that require access to an off-chip memory. The extended HLS design aid generates parallel on-chip multi-cache architectures. It uses the disjointness property of memory accesses to support non-overlapping memory regions by private caches. It also identifies regions which are shared after parallelisation and which are supported by parallel caches with a coherency mechanism and synchronisation, resulting in automatically specialised memory systems. We show up to 15x acceleration from heap partitioning, parallelisation and the insertion of the custom cache system in demonstrably practical applications.Open Acces