Some investigations into the numerical solution of initial value problems in ordinary differential equations

PhD ThesisIn this thesis several topics in the numerical solution of the initial value problem in first-order ordinary diff'erentlal equations are investigated, Consideration is given initially to stiff differential equations and their solution by stiffly-stable linear multistep methods which incorporate second derivative terms. Attempts are made to increase the size of the stability regions for these methods both by particular choices for the third characteristic polynomial and by the use of optimization techniques while investigations are carried out regarding the capabilities of a high order method. Subsequent work is concerned with the development of Runge-Kutta methods which include second-derivative terms and are implicit with respect to y rather than k. Methods of order three and four are proposed which are L-stable. The major part of the thesis is devoted to the establishment of recurrence relations for operators associated with linear multistep methods which are based on a non-polynomial representation of the theoretical solution. A complete set of recurrence relations is developed for both implicit and explicit multistep methods which are based on a representation involving a polynomial part and any number of arbitrary functions. The amount of work involved in obtaining mulc iste, :ne::l'lJds by this technique is considered and criteria are proposed to Jecide when this particular method of derivation should be em~loyed. The thesis is conclud~d by using Prony's method to develop one-step methods and multistep methods which are exponentially adaptive and as such can be useful in obtaining solutions to problems which are exponential in nature

Circuit simulation using distributed waveform relaxation techniques

Simulation plays an important role in the design of integrated circuits. Due to high costs and large delays involved in their fabrication, simulation is commonly used to verify functionality and to predict performance before fabrication. This thesis describes analysis, implementation and performance evaluation of a distributed memory parallel waveform relaxation technique for the electrical circuit simulation of MOS VLSI circuits. The waveform relaxation technique exhibits inherent parallelism due to the partitioning of a circuit into a number of sub-circuits. These subcircuits can be concurrently simulated on parallel processors. Different forms of parallelism in the direct method and the waveform relaxation technique are studied. An analysis of single queue and distributed queue approaches to implement parallel waveform relaxation on distributed memory machines is performed and their performance implications are studied. The distributed queue approach selected for exploiting the coarse grain parallelism across sub-circuits is described. Parallel waveform relaxation programs based on Gauss-Seidel and Gauss-Jacobi techniques are implemented using a network of eight Transputers. Static and dynamic load balancing strategies are studied. A dynamic load balancing algorithm is developed and implemented. Results of parallel implementation are analyzed to identify sources of bottlenecks. This thesis has demonstrated the applicability of a low cost distributed memory multi-computer system for simulation of MOS VLSI circuits. Speed-up measurements prove that a five times improvement in the speed of calculations can be achieved using a full window parallel Gauss-Jacobi waveform relaxation algorithm. Analysis of overheads shows that load imbalance is the major source of overhead and that the fraction of the computation which must be performed sequentially is very low. Communication overhead depends on the nature of the parallel architecture and the design of communication mechanisms. The run-time environment (parallel processing framework) developed in this research exploits features of the Transputer architecture to reduce the effect of the communication overhead by effectively overlapping computation with communications, and running communications processes at a higher priority. This research will contribute to the development of low cost, high performance workstations for computer-aided design and analysis of VLSI circuits