Reconfiguration based built-in self-test for analogue front-end circuits

Previous work has shown that it is feasible to implement a fully digital test evaluation function to realise partial self-test on an automatic gain control circuit (AGC). This paper extends the technique to INL, DNL, offset & gain error testing of analogue to digital converters (ADC's). It also shows how the same function can be used to test an AGC / ADC pair. An extension to full self-test is also proposed by the on-chip generation of input stimuli through reconfiguration of existing functions

Phase Locked Loop Test Methodology

Phase locked loops are incorporated into almost every large-scale mixed signal and digital system on chip (SOC). Various types of PLL architectures exist including fully analogue, fully digital, semi-digital, and software based. Currently the most commonly used PLL architecture for SOC environments and chipset applications is the Charge-Pump (CP) semi-digital type. This architecture is commonly used for clock synthesis applications, such as the supply of a high frequency on-chip clock, which is derived from a low frequency board level clock. In addition, CP-PLL architectures are now frequently used for demanding RF (Radio Frequency) synthesis, and data synchronization applications. On chip system blocks that rely on correct PLL operation may include third party IP cores, ADCs, DACs and user defined logic (UDL). Basically, any on-chip function that requires a stable clock will be reliant on correct PLL operation. As a direct consequence it is essential that the PLL function is reliably verified during both the design and debug phase and through production testing. This chapter focuses on test approaches related to embedded CP-PLLs used for the purpose of clock generation for SOC. However, methods discussed will generally apply to CP-PLLs used for other applications

Dependable reconfigurable multi-sensor poles for security

Wireless sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical [1]. An example of a multi-sensor pole is shown. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. \u

A new BIST scheme for low-power and high-resolution DAC testing

A BIST scheme for testing on chip DAC is presented in this paper. We discuss the generation of on chip testing stimuli and the measurement of digital signals with a narrow-band digital filter. We validate the scheme with software simulation and point out the possibility of ADC BIST with verified DACicus-journals

Analog sinewave signal generators for mixed-signal built-in test applications

This work presents a technique for the generation of analog sinusoidal signals with high spectral quality and reduced circuitry resources. Two integrated demonstrators are presented to show the feasibility of the approach. The proposed generation technique is based on a modified analog filter that provides a sinusoidal output as the response to a DC input. It has the attributes of digital programming and control, low area overhead, and low design effort, which make this approach very suitable as test stimulus generator for built-in test applications. The demonstrators—a continuous-time generator and a discrete-time one—have been integrated in a standard 0.35 μm CMOS technology. Simulation results and experimental measurements in the lab are provided, and the obtained performance is compared to current state-of-the-art on-chip generation strategies.Gobierno de España TEC2007-68072/MIC, TSI-020400-2008-71/MEDEA+2A105, CATRENE CT302Junta de Andalucía P09-TIC-538

A BIST solution for frequency domain characterization of analog circuits

This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1storder ÓÄ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35ìm-3.3V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of [email protected] (1MHz clock) has been demonstrated.Gobierno de España TEC2007-68072/MIC, TSI 020400- 2008-71Catrene European Project 2A105SR

FPGA ARCHITECTURE AND VERIFICATION OF BUILT IN SELF-TEST (BIST) FOR 32-BIT ADDER/SUBTRACTER USING DE0-NANO FPGA AND ANALOG DISCOVERY 2 HARDWARE

The integrated circuit (IC) is an integral part of everyday modern technology, and its application is very attractive to hardware and software design engineers because of its versatility, integration, power consumption, cost, and board area reduction. IC is available in various types such as Field Programming Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), System on Chip (SoC) architecture, Digital Signal Processing (DSP), microcontrollers (μC), and many more. With technology demand focused on faster, low power consumption, efficient IC application, design engineers are facing tremendous challenges in developing and testing integrated circuits that guaranty functionality, high fault coverage, and reliability as the transistor technology is shrinking to the point where manufacturing defects of ICs are affecting yield which associates with the increased cost of the part. The competitive IC market is pressuring manufactures of ICs to develop and market IC in a relatively quick turnaround which in return requires design and verification engineers to develop an integrated self-test structure that would ensure fault-free and the quality product is delivered on the market. 70-80% of IC design is spent on verification and testing to ensure high quality and reliability for the enduser. To test complex and sophisticated IC designs, the verification engineers must produce laborious and costly test fixtures which affect the cost of the part on the competitive market. To avoid increasing the part cost due to yield and test time to the end-user and to keep up with the competitive market many IC design engineers are deviating from complex external test fixture approach and are focusing on integrating Built-in Self-Test (BIST) or Design for Test (DFT) techniques onto IC’s which would reduce time to market but still guarantee high coverage for the product. Understanding the BIST, the architecture, as well as the application of IC, must be understood before developing IC. The architecture of FPGA is elaborated in this paper followed by several BIST techniques and applications of those BIST relative to FPGA, SoC, analog to digital (ADC), or digital to analog converters (DAC) that are integrated on IC. Paper is concluded with verification of BIST for the 32-bit adder/subtracter designed in Quartus II software using the Analog Discovery 2 module as stimulus and DE0-NANO FPGA board for verification

Built-in-self-test of RF front-end circuitry

Fuelled by the ever increasing demand for wireless products and the advent of deep submicron CMOS, RF ICs have become fairly commonplace in the semiconductor market. This has given rise to a new breed of Systems-On-Chip (SOCs) with RF front-ends tightly integrated along with digital, analog and mixed signal circuitry. However, the reliability of the integrated RF front-end continues to be a matter of significant concern and considerable research. A major challenge to the reliability of RF ICs is the fact that their performance is also severely degraded by wide tolerances in on-chip passives and package parasitics, in addition to process related faults. Due to the absence of contact based testing solutions in embedded RF SOCs (because the very act of probing may affect the performance of the RF circuit), coupled with the presence of very few test access nodes, a Built In Self Test approach (BiST) may prove to be the most efficient test scheme. However due to the associated challenges, a comprehensive and low-overhead BiST methodology for on-chip testing of RF ICs has not yet been reported in literature. In the current work, an approach to RF self-test that has hitherto been unexplored both in literature and in the commercial arena is proposed. A sensitive current monitor has been used to extract variations in the supply current drawn by the circuit-under-test (CUT). These variations are then processed in time and frequency domain to develop signatures. The acquired signatures can then be mapped to specific behavioral anomalies and the locations of these anomalies. The CUT is first excited by simple test inputs that can be generated on-chip. The current monitor extracts the corresponding variations in the supply current of the CUT, thereby creating signatures that map to various performance metrics of the circuit. These signatures can then be post-processed by low overhead on-chip circuitry and converted into an accessible form. To be successful in the RF domain any BIST architecture must be minimally invasive, reliable, offer good fault coverage and present low real estate and power overheads. The current-based self-test approach successfully addresses all these concerns. The technique has been applied to RF Low Noise Amplifiers, Mixers and Voltage Controlled Oscillators. The circuitry and post-processing techniques have also been demonstrated in silicon (using the IBM 0.25 micron RF CMOS process). The entire self-test of the RF front-end can be accomplished with a total test time of approximately 30µs, which is several orders of magnitude better than existing commercial test schemes