151 research outputs found
CYBERSECURITY FOR INTELLECTUAL PROPERTY: DEVELOPING PRACTICAL FINGERPRINTING TECHNIQUES FOR INTEGRATED CIRCUITRY
The system on a chip (SoC) paradigm for computing has become more prevalent in modern society. Because of this, reuse of different functional integrated circuits (ICs), with standardized inputs and outputs, make designing SoC systems easier. As a result, the theft of intellectual property for different ICs has become a highly profitable business. One method of theft-prevention is to add a signature, or fingerprint, to ICs so that they may be tracked after they are sold. The contribution of this dissertation is the creation and simulation of three new fingerprinting methods that can be implemented automatically during the design process. In addition, because manufacturing and design costs are significant, three of the fingerprinting methods presented, attempt to alleviate costs by determining the fingerprint in the post-silicon stage of the VLSI design cycle.
Our first two approaches to fingerprint ICs, are to use Observability Donât Cares (ODCs) and Satisfiability Donât Cares (SDCs), which are almost always present in ICs, to hide our fingerprint. ODCs cause an IC to ignore certain internal signals, which we can utilize to create fingerprints that have a minimal performance overhead. Using a heuristic approach, we are also able to choose the overhead the gate will have by removing some fingerprint locations. The experiments show that this work is effective and can provide a large number of fingerprints for more substantial circuits, with a minimal overhead. SDCs are similar to ODCs except that they focus on input patterns, to gates, that cannot exist. For this work, we found a way to quickly locate most of the SDCs in a circuit and depending on the input patterns that we know will not occur, replace the gates to create a fingerprint with a minimal overhead. We also created two methods to implement this SDC fingerprinting method, each with their own advantages and disadvantages. Both the ODC and SDC fingerprinting methods can be implemented in the circuit design or physical design of the IC, and finalized in the post-silicon phase, thus reducing the cost of manufacturing several different circuits.
The third method developed for this dissertation was based on our previous work on finite state machine (FSM) protection to generate a fingerprint. We show that we can edit ICs with incomplete FSMs by adding additional transitions from the set of donât care transitions. Although the best candidates for this method are those with unused states and transitions, additional states can be added to the circuit to generate additional donât care transitions and states, useful for generating more fingerprints. This method has the potential for an astronomical number of fingerprints, but the generated fingerprints need to be filtered for designs that have an acceptable design overhead in comparison to the original circuit.
Our fourth and final method for IC fingerprinting utilizes scan-chains which help to monitor the internal state of a sequential circuit. By modifying the interconnects between flip flops in a scan chain we can create unique fingerprints that are easy to detect by the user. These modifications are done after the design for test and during the fabrication stage, which helps reduce redesign overhead. These changes can also be finalized in the post-silicon stage, similar to the work for the ODC and SDC fingerprinting, to minimize manufacturing costs.
The hope with this dissertation is to demonstrate that these methods for generating fingerprints, for ICs, will improve upon the current state of the art. First, these methods will create a significant number of unique fingerprints. Second, they will create fingerprints that have an acceptable overhead and are easy to detect by the developer and are harder to detect or remove by the adversary. Finally, we show that three of the methods will reduce the cost of manufacturing by being able to be implemented in the later stages of their design cycle
Knowledge Based Systems: A Critical Survey of Major Concepts, Issues, and Techniques
This Working Paper Series entry presents a detailed survey of knowledge based systems. After being in a relatively dormant state for many years, only recently is Artificial Intelligence (AI) - that branch of computer science that attempts to have machines emulate intelligent behavior - accomplishing practical results. Most of these results can be attributed to the design and use of Knowledge-Based Systems, KBSs (or ecpert systems) - problem solving computer programs that can reach a level of performance comparable to that of a human expert in some specialized problem domain. These systems can act as a consultant for various requirements like medical diagnosis, military threat analysis, project risk assessment, etc. These systems possess knowledge to enable them to make intelligent desisions. They are, however, not meant to replace the human specialists in any particular domain. A critical survey of recent work in interactive KBSs is reported. A case study (MYCIN) of a KBS, a list of existing KBSs, and an introduction to the Japanese Fifth Generation Computer Project are provided as appendices. Finally, an extensive set of KBS-related references is provided at the end of the report
Exploiting Don\u27t Cares to Enhance Functional Tests
In simulation based design verification, deterministic or pseudo-random tests are used to check functional correctness of a design. In this paper we present a technique generating tests by specifying the donât care inputs in the functional specifications so as to improve their coverage of both design errors and manufacturing faults. The donât cares are chosen to maximize sensitization of signals in the circuit. The tests generated in this way require only a fraction of pseudo-exhaustive test patterns to achieve a high multiplicity of fault coverage
N-variant Hardware Design
The emergence of lightweight embedded devices imposes stringent constraints on
the area and power of the circuits used to construct them. Meanwhile, many of
these embedded devices are used in applications that require diversity and flexibility
to make them secure and adaptable to the fluctuating workload or variable fabric.
While field programmable gate arrays (FPGAs) provide high flexibility, the use of
application specific integrated circuits (ASICs) to implement such devices is more
appealing because ASICs can currently provide an order of magnitude less area and
better performance in terms of power and speed. My proposed research introduces the
N-variant hardware design methodology that adds the sufficient flexibility needed by
such devices while preserving the performance and area advantages of using ASICs.
The N-variant hardware design embeds different variants of the design control
part on the same IC to provide diversity and flexibility. Because the control circuitry
usually represents a small fraction of the whole circuit, using multiple versions of the
control circuitry is expected to have a low overhead. The objective of my thesis is to
formulate a method that provides the following advantages: (i) ease of integration in
the current ASIC design flow, (ii) minimal impact on the performance and area of the
ASIC design, and (iii) providing a wide range of applications for hardware security
and tuning the performance of chips either statically (e.g., post-silicon optimization)
or dynamically (at runtime). This is achieved by adding diversity at two orthogonal
levels: (i) state space diversity, and (ii) scheduling diversity. State space diversity
expands the state space of the controller. Using state space diversity, we introduce
an authentication mechanism and the first active hardware metering schemes. On the
other hand, scheduling diversity is achieved by embedding different control schedules
in the same design. The scheduling diversity can be spatial, temporal, or a hybrid
of both methods. Spatial diversity is achieved by implementing multiple control
schedules that use various parts of the chip at different rates. Temporal diversity
provides variants of the controller that can operate at unequal speeds. A hybrid of
both spatial and temporal diversities can also be implemented. Scheduling diversity
is used to add the flexibility to tune the performance of the chip. An application
of the thermal management of the chip is demonstrated using scheduling diversity.
Experimental results show that the proposed method is easy to integrate in the current
ASIC flow, has a wide range of applications, and incurs low overhead
Modelling, safety verification and design of discrete/continuous processing systems.
Imperial Users onl
The Automatic Synthesis of Fault Tolerant and Fault Secure VLSI Systems
This thesis investigates the design of fault tolerant and fault secure (FTFS)
systems within the framework of silicon compilation. Automatic design modification
is used to introduce FTFS characteristics into a design. A taxonomy
of FTFS techniques is introduced and is used to identify a number of features
which an "automatic design for FTFS" system should exhibit.
A silicon compilation system, Chip Churn 2 (CC2), has been implemented
and has been used to demonstrate the feasibility of automatic design of FTFS
systems. The CC2 system provides a design language, simulation facilities and
a back-end able to produce CMOS VLSI designs. A number of FTFS design
methods have been implemented within the CC2 environment; these methods
range from triple modular redundancy to concurrent parity code checking. The
FTFS design methods can be applied automatically to general designs in order
to realise them as FTFS systems.
A number of example designs are presented; these are used to illustrate
the FTFS modification techniques which have been implemented. Area results
for CMOS devices are presented; this allows the modification methods to be
compared. A number of problems arising from the methods are highlighted and
some solutions suggested
Security through Obscurity: Layout Obfuscation of Digital Integrated Circuits using Don't Care Conditions
Contemporary integrated circuits are designed and manufactured in a globalized environment leading to concerns of piracy, overproduction and counterfeiting. One class of techniques to combat these threats is circuit obfuscation which seeks to modify the gate-level (or structural) description of a circuit without affecting its functionality in order to increase the complexity and cost of reverse engineering. Most of the existing circuit obfuscation methods are based on the insertion of additional logic (called âkey gatesâ) or camouflaging existing gates in order to make it difficult for a malicious user to get the complete layout information without extensive computations to determine key-gate values. However, when the netlist or the circuit layout, although camouflaged, is available to the attacker, he/she can use advanced logic analysis and circuit simulation tools and Boolean SAT solvers to reveal the unknown gate-level information without exhaustively trying all the input vectors, thus bringing down the complexity of reverse engineering. To counter this problem, some âprovably secureâ logic encryption algorithms that emphasize methodical selection of camouflaged gates have been proposed previously in literature [1,2,3]. The contribution of this paper is the creation and simulation of a new layout obfuscation method that uses don't care conditions. We also present proof-of-concept of a new functional or logic obfuscation technique that not only conceals, but modifies the circuit functionality in addition to the gate-level description, and can be implemented automatically during the design process. Our layout obfuscation technique utilizes donât care conditions (namely, Observability and Satisfiability Donât Cares) inherent in the circuit to camouflage selected gates and modify sub-circuit functionality while meeting the overall circuit specification. Here, camouflaging or obfuscating a gate means replacing the candidate gate by a 4X1 Multiplexer which can be configured to perform all possible 2-input/ 1-output functions as proposed by Bao et al. [4]. It is important to emphasize that our approach not only obfuscates but alters sub-circuit level functionality in an attempt to make IP piracy difficult. The choice of gates to obfuscate determines the effort required to reverse engineer or brute force the design. As such, we propose a method of camouflaged gate selection based on the intersection of output logic cones. By choosing these candidate gates methodically, the complexity of reverse engineering can be made exponential, thus making it computationally very expensive to determine the true circuit functionality. We propose several heuristic algorithms to maximize the RE complexity based on donât care based obfuscation and methodical gate selection. Thus, the goal of protecting the design IP from malicious end-users is achieved. It also makes it significantly harder for rogue elements in the supply chain to use, copy or replicate the same design with a different logic. We analyze the reverse engineering complexity by applying our obfuscation algorithm on ISCAS-85 benchmarks. Our experimental results indicate that significant reverse engineering complexity can be achieved at minimal design overhead (average area overhead for the proposed layout obfuscation methods is 5.51% and average delay overhead is about 7.732%). We discuss the strengths and limitations of our approach and suggest directions that may lead to improved logic encryption algorithms in the future.
References:
[1] R. Chakraborty and S. Bhunia, âHARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection,â IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 10, pp. 1493â1502, 2009.
[2] J. A. Roy, F. Koushanfar, and I. L. Markov, âEPIC: Ending Piracy of Integrated Circuits,â in 2008 Design, Automation and Test in Europe, 2008, pp. 1069â1074.
[3] J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, âSecurity Analysis of Integrated Circuit Camouflaging,â ACM Conference on Computer Communications and Security, 2013.
[4] Bao Liu, Wang, B., "Embedded reconfigurable logic for ASIC design obfuscation against supply chain attacks,"Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014 , vol., no., pp.1,6, 24-28 March 2014
The Fifth NASA Symposium on VLSI Design
The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design
Geostationary Coastal and Air Pollution Events (GeoCAPE) Filter Radiometer (FR)
The GeoCAPE Filter Radiometer (FR) Study is a different instrument type than all of the previous IDL GeoCape studies. The customer primary goals are to keep mass, volume and cost to a minimum while meeting the science objectives and maximizing flight opportunities by fitting on the largest number of GEO accommodations possible. Minimize total mission costs by riding on a commercial GEO satellite. For this instrument type, the coverage rate, km 2 min, was significantly increased while reducing the nadir ground sample size to 250m. This was accomplished by analyzing a large 2d area for each integration period. The field of view will be imaged on a 4k x 4k detector array of 15 micrometer pixels. Each ground pixel is spread over 2 x 2 detector pixels so the instantaneous field of view (IFOV) is 2048 X 2048 ground pixels. The baseline is, for each field of view 50 sequential snapshot images are taken, each with a different filter, before indexing the scan mirror to the next IFOV. A delta would be to add additional filters
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