Barrel Shifter Physical Unclonable Function Based Encryption

Physical Unclonable Functions (PUFs) are circuits designed to extract physical randomness from the underlying circuit. This randomness depends on the manufacturing process. It differs for each device enabling chip-level authentication and key generation applications. We present a protocol utilizing a PUF for secure data transmission. Parties each have a PUF used for encryption and decryption; this is facilitated by constraining the PUF to be commutative. This framework is evaluated with a primitive permutation network - a barrel shifter. Physical randomness is derived from the delay of different shift paths. Barrel shifter (BS) PUF captures the delay of different shift paths. This delay is entangled with message bits before they are sent across an insecure channel. BS-PUF is implemented using transmission gates; their characteristics ensure same-chip reproducibility, a necessary property of PUFs. Post-layout simulations of a common centroid layout 8-level barrel shifter in 0.13 {\mu}m technology assess uniqueness, stability and randomness properties. BS-PUFs pass all selected NIST statistical randomness tests. Stability similar to Ring Oscillator (RO) PUFs under environment variation is shown. Logistic regression of 100,000 plaintext-ciphertext pairs (PCPs) failed to successfully model BS- PUF behavior

An Energy Feedback System for the MIT/Bates Linear Accelerator

We report the development and implementation of an energy feedback system for the MIT/Bates Linear Accelerator Center. General requirements of the system are described, as are the specific requirements, features, and components of the system unique to its implementation at the Bates Laboratory. We demonstrate that with the system in operation, energy fluctuations correlated with the 60 Hz line voltage and with drifts of thermal origin are reduced by an order of magnitude

A Wideband CMOS Linear Digital Phase Rotator

This paper presents a 10-bit wideband Cartesian phase rotator with a novel linear digital VGA implemented in a 0.13um CMOS process. The VGA topology is robust to device modeling uncertainties and PVT variations. The system provides 7.8dB voltage gain with -3dB bandwidth of 7.6GHz. A maximum phase error of 2º has been achieved for a phase shifting range of 360º with 32 phase steps of 11.25º. The capability to compensate for mismatched quadrature inputs is also demonstrated

System-Level Integrated Circuit (SLIC) development for phased array antenna applications

A microwave/millimeter wave system-level integrated circuit (SLIC) being developed for use in phased array antenna applications is described. The program goal is to design, fabricate, test, and deliver an advanced integrated circuit that merges radio frequency (RF) monolithic microwave integrated circuit (MMIC) technologies with digital, photonic, and analog circuitry that provide control, support, and interface functions. As a whole, the SLIC will offer improvements in RF device performance, uniformity, and stability while enabling accurate, rapid, repeatable control of the RF signal. Furthermore, the SLIC program addresses issues relating to insertion of solid state devices into antenna systems, such as the reduction in number of bias, control, and signal lines. Program goals, approach, and status are discussed

System architecture of MMIC-based large aperture arrays for space application

The persistent trend to use millimeter-wave frequencies for satellite communications presents the challenge to design large-aperture phased arrays for space applications. These arrays, which comprise 100 to 10,000 elements, are now possible due to the advent of lightwave technology and the availability of monolithic microwave integrated circuits. In this paper, system aspects of optically controlled array design are studied. In particular, two architectures for a 40 GHz array are outlined, and the main system-related issues are examined: power budget, synchronization in frequency and phase, and stochastic effects

Development of a broadband and squint-free Ku-band phased array antenna system for airborne satellite communications

Novel avionic communication systems are required for various purposes, for example to increase the flight safety and operational integrity as well as to enhance the quality of service to passengers on board. To serve these purposes, a key technology that is essential to be developed is an antenna system that can provide broadband connectivity within aircraft cabins at an affordable price. Currently, in the European Commission (EC) 7th Framework Programme SANDRA project (SANDRA, 2011), a development of such an antenna system is being carried out. The system is an electronically-steered phased-array antenna (PAA) with a low aerodynamic profile. The reception of digital video broadcasting by satellite (DVB-S) signal which is in the frequency range of 10.7-12.75 GHz (Ku-band) is being considered. In order to ensure the quality of service provided to the passengers, the developed antenna should be able to receive the entire DVB-S band at once while complying with the requirements of the DVB-S system (Morello & Mignone, 2006). These requirements, as will be explained later, dictate a broadband antenna system where the beam is squint-free, i.e. no variation of beam pointing direction for all the frequencies in the desired band. Additionally, to track the satellite, the seamless tunability of the beam pointing direction of this antenna is also required. In this work, a concept of optical beamforming (Riza & Thompson, 1997) is implemented to provide a squint-free beam over the entire Ku-band for all the desired pointing directions. The optical beamformer itself consists of continuously tunable optical delay lines that enable seamless tunability of the beam pointing direction

Surface acoustic wave stabilized oscillators

Four areas of surface acoustic wave (SAW) controlled oscillators were investigated and a number of 401.2 MHz oscillators were constructed that showed improved performance. Aging studies on SAW devices packaged in HC36/U cold weld enclosures produced frequency drifts as low as 0.4 ppm in 35 weeks and drift rates well under 0.5 ppm/year. Temperature compensation circuits have substantially improved oscillator temperature stability, with a deviation of + or - 4 ppm observed over the range -45 C to + 40 C. High efficiency amplifiers were constructed for SAW oscillators and a dc to RF efficiency of 44 percent was obtained for an RF output of 25 mW. Shock and vibration tests were made on four oscillators and all survived 500 G shock pulses unchanged. Only when white noise vibration (20 Hz to 2000 Hz) levels of 20 G's rms were applied did some of the devices fail

I/O Master

The I/O Master is an engineering tool designed to let users quickly and efficiently use their computer to interface with embedded devices and sensors. Using a general purpose design, the goal is to make it possible to implement any digital protocol on the I/O Master. With the use of onboard level shifting, differential communication components, peripheral DMA through GPIO and a USB 2.0 High Speed computer interface, the I/O Master is able to implement such a general purpose design with initial implementation of five protocols to verify the design\u27s capabilities. The implementation of a computer-based GUI and underlying framework allows users to easily use the I/O Master with additional flexibility to write custom programs for it. While many characteristics of components were considered for the design, the design lacks quantified information relating to propagation delay of components and response time for some of the electrical safety components. Engineers can use the I/O Master to make the early phases of design faster when there is a need to interface with sensors for testing and analysis. The design of the I/O Master allows for additional protocols to be implemented in the future with only limited changes needed in the software

Buffer Interference Architecture

An up to 3× breakdown voltage tristate capable integrated circuit CMOS buffer includes a level shifter circuit and a driver circuit. The driver stage includes a series connected n-channel and p-channel cascode stacks, each including at least three transistors. Dynamic gate biasing is provided for the third n-channel and p-channel cascode transistors to prevent voltage overstress of the cascode transistors. The level shifter circuit includes at least one pseudo N-MOS inverter including an input transistor, a protective cascode stack including at least one n-channel cascode transistor, and a load transistor. The level shifter provides at least one voltage shifted input signal to the driver