Investigation into synchronization for partial response signals and the development of a clock recovery scheme for 49QPRS signals

ThesisData communication is used increasingly in modern society. It is against this background that research is conducted worldwide toward the improvement of existing, as well as the development of new, improved communication techniques. Correlative encoding of data before transmission IS a very frequency-effective communication technique. The extent to which any communication technique is used, however, is dependent on a wide variety of factors. This study regarding the synchronisation of 49QPRS signals was undertaken with this in mind. Since digital signal processing (DSP) is used increasingly in modern communication systems, both a data transmitter and receiver were implemented by making use of this technique. Not only would this result in a system with all the desirable characteristics inherent to DSP, but, by making limited changes to the supporting software, the evaluation of a wide variety of alternatives became feasible. During the study a system making use of a pilot tone at one third the frequency of the carrier frequency was developed. The receiver recovers this signal by means of DSP techniques and its frequency is tripled. The phase of this recovered signal is crosscorrelated every 650 ~s in time with a locally generated signal of the correct frequency - and the phase of the locally generated signal is adjusted accordingly. It was found that the accuracy and stability of the locally generated signal were such that sufficient synchronisation was obtained in this manner. The quality of synchronisation is a function of the level of the pilot tone and if this tone should decrease to below a certain value, unacceptably large phase adjustments have to be made. This results in a senous degradation of the spectral purity of the recovered signal. However, the system as described exhibits extremely good noise immunity. During the development of the clock frequency recovery system, a baseband filter with a unique frequency response was defined. Making use of this, in conjunction with a limited amount of pre-processing, and an absolute value rectifier, recovery of the clock frequency becomes possible. In order to limit the amount of processing by the receiver, the baseband filter was implemented in its entirety in the transmitter. The recovered signal showed a moderate amount of amplitude variation, but an extremely stable synchronising signal could be derived from this. During the study both levels of synchronisation required by a hypothetical 49QPRS data communication system were therefore investigated fully and solutions found

Adaptive equalizers for multipath compensation in digital microwave communications

SIGLEAvailable from British Library Document Supply Centre- DSC:D82998 / BLDSC - British Library Document Supply CentreGBUnited Kingdo

Real-time Digital Signal Processing for Software-defined Optical Transmitters and Receivers

A software-defined optical Tx is designed and demonstrated generating signals with various formats and pulse-shapes in real-time. Special pulse-shapes such as OFDM or Nyquist signaling were utilized resulting in a highly efficient usage of the available fiber channel bandwidth. This was achieved by parallel data processing with high-end FPGAs. Furthermore, highly efficient Rx algorithms for carrier and timing recovery as well as for polarization demultiplexing were developed and investigated

The development of a novel modem structure for connection of rural to diginet

Includes bibliographical references.This thesis investigates the use of partial response signalling as a modulation scheme in a modem structure. The modem structure consists of transmitter modulation and receiver demodulation sections only. The modem is designed to operate at data rates of 2400, 4800 and 9600 bps. The signalling format replaces the CCITT Recommendation V.29 format. The transmitted signal is required to conform to the bandwidth limitations of CCITT Recommendation M.1020 leased telephone circuits

Nuevas implementaciones digitales de sincronismos de BIT y portadora en Módem CPM

Las técnicas digitales aplicadas a receptores y transmisores están imponiéndose a las convencionales técnicas analógicas por las diversas ventajas que supone. En este sentido se impone una investigación con el fin de desarrollar dichas técnicas o mejorarlas en algún aspecto. La idea principal que engloba esta Tesis Doctoral es precisamente la indagación en algunas de dichas técnicas, su análisis, caracterización y aplicación a dos casos concretos. En un primer momento se han caracterizado dos canales de comunicaciones donde se pretende hacer uso de las técnicas a desarrollar. Este es un aspecto importante para conocer las condiciones reales en que deberán operar los algoritmos y cómo pueden verse afectados. Los canales que se caracterizan corresponden al establecido para satélites de órbita baja y el formado por las líneas de distribución de media tensión. En segundo lugar se ha realizado una descripción del tipo de modulación que se pretende emplear en los canales (GMSK) y se ha tratado de obtener una estructura del receptor con la menor complejidad posible. Basándose en una descripción de la modulación mediante una aproximación que da lugar a un modelo lineal, se desarrolla un receptor lineal de estructura sencilla y con unas prestaciones razonables, suponiendo una gran ventaja. Una vez descrita la estructura del receptor en el cual se van a emplear los algoritmos, se tratan dos aspectos cruciales en los receptores: la sincronización de portadora y el sincronismo de bit. Las técnicas que se desarrollan parten de la idea de su integración en un receptor totalmente digital. Son técnicas de procesado digital de señales. Se aborda el problema de la sincronización de portadora dando como solución diversos algoritmos que operan basándose en diferentes principios y obtienen diferentes características. Se destacan las ventajas e inconvenientes de cada uno de ellos y se presentan resultados de su funcionamiento. Respecto a la sincronización de bit se aborda el caso del empleo de interpoladores basados en la interpolación matemática para tal fin. Se trata de una técnica de cambio de velocidad de muestreo de forma dinámica para que las muestras de salida estén situadas en los instantes de muestreo óptimos. El interpolador lleva asociados un detector de error de sincronismo de bit y un sistema de control del interpolador. En el caso del detector de error se ha partido de la premisa de obtener un detector sencillo, de baja carga computacional y eficiente. El algoritmo se ha basado en el cruce por cero de la señal en las alternancias