A FRACTIONAL DELAY FIR FILTER BASED ON LAGRANGE INTERPOLATION OF FARROW STRUCTURE

An efficient implementation technique for the Lagrange interpolation is derived. This formulation called the Farrow structure leads to a version of Lagrange interpolation that is well suited to time varying FD filtering. Lagrange interpolation is mostly used for fractional delay approximation as it can be used for increasing the sampling rate of signals and systems. Lagrange interpolation is one of the representatives for a class of polynomial interpolation techniques. The computational cost of this structure is reduced as the number of multiplications are minimised in the new structure when compared with the conventional structure

Envelope and phase delays correction in an EER radio architecture

International audienceThis article deals with synchronization in the Envelope Elimination and Restoration (EER) type of transmitter architecture. To illustrate the performances of such solution, we choose to apply this architecture to a 64 carriers 16QAM modulated OFDM. We first introduce the problematic of the realisation of a highly linear transmitter.We then present the Envelope Elimination and Restoration solution and draw attention to its major weakness: a high sensitivity to desynchronization between the phase and envelope signal paths. To address this issue, we propose an adaptive synchronization algorithm relying on a feedback loop, a LeastMean Square formulation and involving an interpolation step. It enables the correction of delay mismatches and tracking of possible variations. We demonstrate that the quality of the interpolator has a direct impact on Error Vector Magnitude (EVM) value and output spectrum. Implementation details are provided along with an analysis of the behaviour and performances of the method. We present HPADS and Matlab simulation results and then focus on the enhancement of the transmitter performances using the proposed algorithm

Optimal design of all-pass variable fractional-delay digital filters

This paper presents a computational method for the optimal design of all-pass variable fractional-delay (VFD) filters aiming to minimize the squared error of the fractional group delay subject to a low level of squared error in the phase response. The constrained optimization problem thus formulated is converted to an unconstrained least-squares (LS) optimization problem which is highly nonlinear. However, it can be approximated by a linear LS optimization problem which in turn simply requires the solution of a linear system. The proposed method can efficiently minimize the total error energy of the fractional group delay while maintaining constraints on the level of the error energy of the phase response. To make the error distribution as flat as possible, a weighted LS (WLS) design method is also developed. An error weighting function is obtained according to the solution of the previous constrained LS design. The maximum peak error is then further reduced by an iterative updating of the error weighting function. Numerical examples are included in order to compare the performance of the filters designed using the proposed methods with those designed by several existing methods

Digital Filters

The new technology advances provide that a great number of system signals can be easily measured with a low cost. The main problem is that usually only a fraction of the signal is useful for different purposes, for example maintenance, DVD-recorders, computers, electric/electronic circuits, econometric, optimization, etc. Digital filters are the most versatile, practical and effective methods for extracting the information necessary from the signal. They can be dynamic, so they can be automatically or manually adjusted to the external and internal conditions. Presented in this book are the most advanced digital filters including different case studies and the most relevant literature

A Wide Band Adaptive All Digital Phase Locked Loop With Self Jitter Measurement And Calibration

The expanding growth of mobile products and services has led to various wireless communication standards that employ different spectrum bands and protocols to provide data, voice or video communication services. Software deffned radio and cognitive radio are emerging techniques that can dynamically integrate various standards to provide seamless global coverage, including global roaming across geographical regions, and interfacing with different wireless networks. In software deffned radio and cognitive radio, one of the most critical RF blocks that need to exhibit frequency agility is the phase lock loop (PLL) frequency synthesizer. In order to access various standards, the frequency synthesizer needs to have wide frequency tuning range, fast tuning speed, and low phase noise and frequency spur. The traditional analog charge pump frequency synthesizer circuit design is becoming diffcult due to the continuous down-scalings of transistor feature size and power supply voltage. The goal of this project was to develop an all digital phase locked loop (ADPLL) as the alternative solution technique in RF transceivers by taking advantage of digital circuitry\u27s characteristic features of good scalability, robustness against process variation and high noise margin. The targeted frequency bands for our ADPLL design included 880MHz-960MHz, 1.92GHz-2.17GHz, 2.3GHz-2.7GHz, 3.3GHz-3.8GHz and 5.15GHz-5.85GHz that are used by wireless communication standards such as GSM, UMTS, bluetooth, WiMAX and Wi-Fi etc. This project started with the system level model development for characterizing ADPLL phase noise, fractional spur and locking speed. Then an on-chip jitter detector and parameter adapter was designed for ADPLL to perform self-tuning and self-calibration to accomplish high frequency purity and fast frequency locking in each frequency band. A novel wide band DCO is presented for multi-band wireless application. The proposed wide band adaptive ADPLL was implemented in the IBM 0.13µm CMOS technology. The phase noise performance, the frequency locking speed as well as the tuning range of the digitally controlled oscillator was assessed and agrees well with the theoretical analysis