Testing high resolution SD ADC’s by using the noise transfer function

A new solution to improve the testability of high resolution SD Analogue to Digital Converters (SD ADC’s) using the quantizer input as test node is described. The theoretical basis for the technique is discussed and results from high level simulations for a 16 bit, 4th order, audio ADC are presented. The analysis demonstrates the potential to reduce the computational effort associated with test response analysis versus conventional techniques

On-the-fly computation method in field-programmable gate array for analog-to-digital converter linearity testing

© 2018 Published by ITB Journal Publisher. This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.Ph.D

Low power digital baseband core for wireless Micro-Neural-Interface using CMOS sub/near-threshold circuit

This thesis presents the work on designing and implementing a low power digital baseband core with custom-tailored protocol for wirelessly powered Micro-Neural-Interface (MNI) System-on-Chip (SoC) to be implanted within the skull to record cortical neural activities. The core, on the tag end of distributed sensors, is designed to control the operation of individual MNI and communicate and control MNI devices implanted across the brain using received downlink commands from external base station and store/dump targeted neural data uplink in an energy efficient manner. The application specific protocol defines three modes (Time Stamp Mode, Streaming Mode and Snippet Mode) to extract neural signals with on-chip signal conditioning and discrimination. In Time Stamp Mode, Streaming Mode and Snippet Mode, the core executes basic on-chip spike discrimination and compression, real-time monitoring and segment capturing of neural signals so single spike timing as well as inter-spike timing can be retrieved with high temporal and spatial resolution. To implement the core control logic using sub/near-threshold logic, a novel digital design methodology is proposed which considers INWE (Inverse-Narrow-Width-Effect), RSCE (Reverse-Short-Channel-Effect) and variation comprehensively to size the transistor width and length accordingly to achieve close-to-optimum digital circuits. Ultra-low-power cell library containing 67 cells including physical cells and decoupling capacitor cells using the optimum fingers is designed, laid-out, characterized, and abstracted. A robust on-chip sense-amp-less SRAM memory (8X32 size) for storing neural data is implemented using 8T topology and LVT fingers. The design is validated with silicon tapeout and measurement shows the digital baseband core works at 400mV and 1.28 MHz system clock with an average power consumption of 2.2 μW, resulting in highest reported communication power efficiency of 290Kbps/μW to date

Design, Fabrication and Veri cation of a Mixed-Signal XY Zone Monitoring Circuit and its Application to a Phase Lock Loop Circuit

El presente proyecto de final de carrera se centra en el diseño, análisis e implementación en silicio de una metodología de test/diagnosis basada en la comparación de firmas digitales generadas a partir de curvas de Lissajous. Se muestra su aplicación para testar la etapa de filtro de un circuito de bucle de enganche de fase (phase lock loop, PLL), así como los resultados experimentales de su implementación en tecnología CMOS de 65 nm. La obtención de las firmas digitales se consigue mediante el uso de un circuito monitor, el cual, a partir de la composición de dos señales periódicas del circuito a analizar, genera, para cada punto de la curva de Lissajous, un valor digital. La utilización de varios monitores con gurados de la manera adecuada permite una completa teselación del plano en diferentes zonas y por tanto, la generación de distintos códigos digitales (firma) a medida que la curva de Lissajous evoluciona en el tiempo. El test del circuito y/o diagnosis del posible defecto se realiza mediante la comparación de la signatura golden o sin defecto y la signatura generada por el circuito testado. Para la comparación de firmas se emplea el concepto de distancia de Hamming entre códigos a modo de métrica de discrepancia. A partir de los valores precalculados de la métrica para cada posible valor del defecto se consigue realizar la diagnosis de este para el parámetro en estudio. El trabajo se enmarca en el diseño de circuitos integrados de muy alta escala de integración usando una tecnología CMOS de actualidad (65 nm). Es por ello que se requieren técnicas de diseño analógico específicas, como lo son las estrategias centroidales para la elaboración de layouts o el correcto modelado de transistores nanométricos. Para esto último se hace uso del modelo Berkeley, el cual, debidamente ajustado a la tecnología empleada, proporciona aproximaciones muy aceptables y con relativa facilidad de uso. Con el objetivo de verificar la metodología de test/diagnosis propuesta, se hace uso de una aplicación Matlab que permite simular el comportamiento del circuito a testar en diferentes situaciones. Es posible excitar el circuito con distintas entradas, cambiar los parámetros de este, introducir defectos, o emplear distintos conjuntos de curvas para teselar el plano. La aplicación resulta fundamental para efectuar el proceso de diagnosis pues relaciona la cantidad de defecto con los valores de discrepancia obtenidos con la métrica definida. Finalmente, se presentan los resultados experimentales obtenidos con el chip fabricado. Se constata el correcto comportamiento de este y la validez de la metodología de test/diagnosis propuesta

Cherenkov Camera and Analysis Development for Highest-Energy Gamma-Ray Astronomy

Imaging atmospheric Cherenkov telescopes are used for the detection of highest-energy γ-rays. This thesis focuses on two experiments equipped with such telescopes: The operating High Energy Stereoscopic System (H.E.S.S.) and the future Cherenkov Telescope Array (CTA). Four of the five H.E.S.S. cameras saw a major electronics upgrade a few years ago enabling improved readout and analysis techniques mainly at the highest energies. The Compact High-Energy Camera (CHEC) is a design for the Small-Sized Telescopes of CTA focusing on the detection of γ-rays with energies exceeding 1 TeV. The first part of the thesis is dedicated to the characterisation of two CHEC prototype cameras developed successively: CHEC-M and CHEC-S. I present results of laboratory and on-telescope measurements for both cameras. In the case of CHEC-S, I focus on those parameters that had been shown to be performance-limiting in CHEC-M and which were therefore addressed in the design iteration for CHEC-S. The second part is devoted to the upgraded H.E.S.S. cameras. I present results of Monte-Carlo simulation studies, analysis developments, and performance measurements using full-waveform readout. In the former case I demonstrate a general consistency between simulations and measurements, in the latter case I show that the use of full-sampled waveform readout improves the performance, especially at the highest energies. In the last part, I present a new analysis of the Galactic γ-ray source HESS J1646–458 which is associated with Westerlund 1, the most massive stellar cluster in our Galaxy