BlackJack: Secure machine learning on IoT devices through hardware-based shuffling

Neural networks are seeing increased use in diverse Internet of Things (IoT) applications such as healthcare, smart homes and industrial monitoring. Their widespread use makes neural networks a lucrative target for theft. An attacker can obtain a model without having access to the training data or incurring the cost of training. Also, networks trained using private data (e.g., medical records) can reveal information about this data. Networks can be stolen by leveraging side channels such as power traces of the IoT device when it is running the network. Existing attacks require operations to occur in the same order each time; an attacker must collect and analyze several traces of the device to steal the network. Therefore, to prevent this type of attack, we randomly shuffle the order of operations each time. With shuffling, each operation can now happen at many different points in each execution, making the attack intractable. However, we show that shuffling in software can leak information which can be used to subvert this solution. Therefore, to perform secure shuffling and reduce latency, we present BlackJack, hardware added as a functional unit within the CPU. BlackJack secures neural networks on IoT devices by increasing the time needed for an attack to centuries, while adding just 2.46% area, 3.28% power and 0.56% latency overhead on an ARM M0+ SoC.Comment: 16 pages, 6 figure

Feature Importance for Black-box Models

Důležitost proměnných je technika, která přiřazuje skóre vstupním proměnným (sloupcům strukturovaných dat) na základě jejich vlivu na predikování cílové proměnné. Sloupce datasetu, které jsou použity jako vstup do algoritmu strojového učení se nazývají proměnné. Některé vtupní proměnné můžou být více důležité než ostatní tím, že více ovlivňují cílovou proměnou. Globální senzitivní analýza přiřazuje hodnoty jednotlivým vstupním proměnným na základě jejich interakcích pri predikci s ohledem na cílovou proměnnou a poskytuje tak skóre pro interpretaci modelů. Cílem této bakalářské práce je popsat metodu Permutační důležitosti proměnných a implementovat tuto metodu do H2O-3 open-source Machine Learning platformy.Feature importance is a technique that assigns a score to input features (tabular data columns) based on the influence of predicting the target feature. The columns of a dataset that servers as an input of the Machine Learning algorithms are called features. Some features may be more important than others giving more influence towards the output. Global Sensitivity Analysis quantifies the importance of model features and their interactions with respect to model output. Assigning different values to the features one at a time provides the user with a mapping score of importance to features to interpret the model. The aim of this bachelor's thesis is to describe Permutation Feature Importance and implement this method to the H2O-3 open-source Machine Learning platform

Implementasi Algoritma Fisher-Yates Untuk Mengacak Soal Ujian Online Penerimaan Mahasiswa Baru (Studi Kasus : Universitas Lancang Kuning Riau)

Ujian merupakan salah satu cara untuk mendapatkan hasil yang berguna untuk mengevaluasi proses pembelajaran dan mengukur taraf pencapaian suatu tujuan pengajaran. Universitas Lancang Kuning (UNILAK) Pekanbaru menggunakan CBT (Computer Based Test) dalam penerimaan mahasiswa baru. Dalam proses pelaksanaan ujian diperlukan sebuah algoritma yang memiliki metode yang menghasilkan permutasi acak sehingga dapat mengurangi kecurangan yang dilakukan oleh peserta ujian CBT.  Algoritma Fisher-Yates Shuffle adalah sebuah algoritma yang menghasilkan permutasi acak dari suatu himpunan terhingga, dengan kata lain untuk mengacak suatu himpunan tersebut. Jika di implementasikan dengan benar maka hasil dari algoritma ini tidak akan berat sebelah sehingga setiap permutasi memiliki kemungkinan yang sama. Proses yang dilakukan algoritma adalah memasukkan atribut soal kedalam scratch (daftar soal yang belum terpilih), lalu membuat  range (jumlah soal yang belum terpilih) kemudian dilakukan proses pengacakan, selanjutnya membentuk roll (untuk sebuah soal yang terpilih dari semua jumlah soal yang ada) kemudian hasil soal yang sudah terpilih dimasukkan kedalam result (hasil dari seluruh soal yang telah dilakukan pengacakan). Dari proses algoritma yang dilakukan mendapatkan hasil perubahan posisi atau urutan soal sehingga didapatkan bahwa setiap peserta ujian yang melakukan ujian pada saat waktu yang bersamaan mendapatkan bentuk soal yang berbeda

A high performance neural network javascript library

Master's Project (M.S.) University of Alaska Fairbanks, 2015This report covers Intellect.js, a new high-performance Artificial Neural Network (ANN) library written in JavaScript and intended for use within a web browser. The library is designed to be easy to use, whilst remaining highly customizable and flexible. A brief history of JavaScript and ANNs is presented, along with decisions made while developing Intellectjs. Lastly, performance benchmarks are provided, including comparisons with existing ANN libraries written in JavaScript. Appendices include a code listing, usage examples, and complete performance data. Intellect.js is available on GitHub under the MIT License. https://github.com/sutekidayo/intellect.j

A Chaotic System and Count Tracking Mechanism-based Dynamic S-Box and Secret Key Generation

In cryptography, Block ciphers use S-Boxes to perform substitution and permutation operations on a data block. S-Boxes provide non-linearity and confusion of bits to the cryptographic algorithms. In addition, secret keys are critical security aspects for encrypting and decrypting messages. The uncertainty and randomness of the secret key and S-boxes used in the algorithm determine the extent of security against any cryptanalysis attack. This paper proposes a new mechanism to dynamically generate a secret key and S-Box each time while sending and receiving the message. These dynamically generated S-Boxes and keys depend on mutually decided security parameters and message transfer history. Furthermore, a new counter-based mechanism is introduced in this paper. These enhancement techniques are applied to the serpent cipher algorithm, and a data transfer simulation is performed to validate the efficacy of the proposed method. We observe that the dynamically generated S-box follows the strict avalanche criteria. We further validate that the encrypted message shows higher sensitivity to the S-box and the secret key in enhanced serpent cipher than the original version. However, to validate our proposed method, we test and analyze the improvements in the Serpent Cipher Algorithm

HARPOCRATES: An Approach Towards Efficient Encryption of Data-at-rest

This paper proposes a new block cipher called HARPOCRATES, which is different from traditional SPN, Feistel, or ARX designs. The new design structure that we use is called the substitution convolution network. The novelty of the approach lies in that the substitution function does not use fixed S-boxes. Instead, it uses a key-driven lookup table storing a permutation of all 8-bit values. If the lookup table is sufficiently randomly shuffled, the round sub-operations achieve good confusion and diffusion to the cipher. While designing the cipher, the security, cost, and performances are balanced, keeping the requirements of encryption of data-at-rest in mind. The round sub-operations are massively parallelizable and designed such that a single active bit may make the entire state (an 8 × 16 binary matrix) active in one round. We analyze the security of the cipher against linear, differential, and impossible differential cryptanalysis. The cipher’s resistance against many other attacks like algebraic attacks, structural attacks, and weak keys are also shown. We implemented the cipher in software and hardware; found that the software implementation of the cipher results in better throughput than many well-known ciphers. Although HARPOCRATES is appropriate for the encryption of data-at-rest, it is also well-suited in data-in-transit environments

Low-Overhead Migration of Read-Only and Read-Mostly Data for Adapting Applications to Hybrid Memory Systems

Memory systems containing different types of memory with varying capacity, latency, and bandwidth are rapidly becoming mainstream. Conventional memory management techniques do not suffice for these systems; they require alternative strategies to appropriately and effectively adapt application memory placement to these heterogeneous memory tiers. Software-based placement and movement strategies are the most desirable due to their flexibility and ease of adoption by end-users. However, there are substantial sources of overhead present when synchronizing low-level data movement with the operating system and running applications.This thesis proposes a novel method of reducing these memory movement overheads on hybrid memory systems. Many data objects are only written to early in their life cycle (i.e. shortly after allocation) and are effectively read-only after these initial writes. If this read-only and read-mostly data is duplicated across memory tiers, as opposed to moved, the application, in many cases, is able to avoid certain types of transfer overhead, such as page table entry (PTE) and MMU cache (TLB) synchronization stalls.This work describes the design and implementation of a kernel module, mtier that implements this optimization on memory that has been explicitly marked as read-only. Our evaluation demonstrates that this approach has the potential to substantially reduce data movement overheads, especially in applications that are multi-threaded and require frequent movement of data, allowing a flexible, software based approach for memory management in hybrid systems

Hardware Architectures for Post-Quantum Cryptography

The rapid development of quantum computers poses severe threats to many commonly-used cryptographic algorithms that are embedded in different hardware devices to ensure the security and privacy of data and communication. Seeking for new solutions that are potentially resistant against attacks from quantum computers, a new research field called Post-Quantum Cryptography (PQC) has emerged, that is, cryptosystems deployed in classical computers conjectured to be secure against attacks utilizing large-scale quantum computers. In order to secure data during storage or communication, and many other applications in the future, this dissertation focuses on the design, implementation, and evaluation of efficient PQC schemes in hardware. Four PQC algorithms, each from a different family, are studied in this dissertation. The first hardware architecture presented in this dissertation is focused on the code-based scheme Classic McEliece. The research presented in this dissertation is the first that builds the hardware architecture for the Classic McEliece cryptosystem. This research successfully demonstrated that complex code-based PQC algorithm can be run efficiently on hardware. Furthermore, this dissertation shows that implementation of this scheme on hardware can be easily tuned to different configurations by implementing support for flexible choices of security parameters as well as configurable hardware performance parameters. The successful prototype of the Classic McEliece scheme on hardware increased confidence in this scheme, and helped Classic McEliece to get recognized as one of seven finalists in the third round of the NIST PQC standardization process. While Classic McEliece serves as a ready-to-use candidate for many high-end applications, PQC solutions are also needed for low-end embedded devices. Embedded devices play an important role in our daily life. Despite their typically constrained resources, these devices require strong security measures to protect them against cyber attacks. Towards securing this type of devices, the second research presented in this dissertation focuses on the hash-based digital signature scheme XMSS. This research is the first that explores and presents practical hardware based XMSS solution for low-end embedded devices. In the design of XMSS hardware, a heterogenous software-hardware co-design approach was adopted, which combined the flexibility of the soft core with the acceleration from the hard core. The practicability and efficiency of the XMSS software-hardware co-design is further demonstrated by providing a hardware prototype on an open-source RISC-V based System-on-a-Chip (SoC) platform. The third research direction covered in this dissertation focuses on lattice-based cryptography, which represents one of the most promising and popular alternatives to today\u27s widely adopted public key solutions. Prior research has presented hardware designs targeting the computing blocks that are necessary for the implementation of lattice-based systems. However, a recurrent issue in most existing designs is that these hardware designs are not fully scalable or parameterized, hence limited to specific cryptographic primitives and security parameter sets. The research presented in this dissertation is the first that develops hardware accelerators that are designed to be fully parameterized to support different lattice-based schemes and parameters. Further, these accelerators are utilized to realize the first software-harware co-design of provably-secure instances of qTESLA, which is a lattice-based digital signature scheme. This dissertation demonstrates that even demanding, provably-secure schemes can be realized efficiently with proper use of software-hardware co-design. The final research presented in this dissertation is focused on the isogeny-based scheme SIKE, which recently made it to the final round of the PQC standardization process. This research shows that hardware accelerators can be designed to offload compute-intensive elliptic curve and isogeny computations to hardware in a versatile fashion. These hardware accelerators are designed to be fully parameterized to support different security parameter sets of SIKE as well as flexible hardware configurations targeting different user applications. This research is the first that presents versatile hardware accelerators for SIKE that can be mapped efficiently to both FPGA and ASIC platforms. Based on these accelerators, an efficient software-hardwareco-design is constructed for speeding up SIKE. In the end, this dissertation demonstrates that, despite being embedded with expensive arithmetic, the isogeny-based SIKE scheme can be run efficiently by exploiting specialized hardware. These four research directions combined demonstrate the practicability of building efficient hardware architectures for complex PQC algorithms. The exploration of efficient PQC solutions for different hardware platforms will eventually help migrate high-end servers and low-end embedded devices towards the post-quantum era