10,130 research outputs found
Validation by Measurements of a IC Modeling Approach for SiP Applications
The growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi
An effective AMS Top-Down Methodology Applied to the Design of a Mixed-SignalUWB System-on-Chip
The design of Ultra Wideband (UWB) mixed-signal SoC for localization applications in wireless personal area networks is currently investigated by several researchers. The complexity of the design claims for effective top-down methodologies. We propose a layered approach based on VHDL-AMS for the first design stages and on an intelligent use of a circuit-level simulator for the transistor-level phase. We apply the latter just to one block at a time and wrap it within the system-level VHDL-AMS description. This method allows to capture the impact of circuit-level design choices and non-idealities on system performance. To demonstrate the effectiveness of the methodology we show how the refinement of the design affects specific UWB system parameters such as bit-error rate and localization estimations
The Future of High Frequency Circuit Design
The cut-off wavelengths of integrated silicon transistors have
exceeded the die sizes of the chips being fabricated with them.
Combined with the ability to integrate billions of transistors on
the same die, this size-wavelength cross-over has produced a
unique opportunity for a completely new class of holistic circuit
design combining electromagnetics, device physics, circuits, and
communication system theory in one place. In this paper, we discuss
some of these opportunities and their associated challenges
in greater detail and provide a few of examples of how they can
be used in practice
Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies
CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections
Impact of crosstalk into high resistivity silicon substrate on the RF performance of SOI MOSFET
Crosstalk propagation through silicon substrate is
a serious limiting factor on the performance of the RF devices
and circuits. In this work, substrate crosstalk into high resistivity
silicon substrate is experimentally analyzed and the
impact on the RF behavior of silicon-on-insulator (SOI) MOS
transistors is discussed. The injection of a 10 V peak-to-peak
single tone noise signal at a frequency of 3 MHz ( fnoise) generates
two sideband tones of *−56 dBm separated by fnoise from
the RF output signal of a partially depleted SOI MOSFET
at 1 GHz and 4.1 dBm. The efficiency of the introduction
of a trap-rich polysilicon layer located underneath the buried
oxide (BOX) of the high resistivity (HR) SOI wafer in the
reduction of the sideband noise tones is demonstrated. An
equivalent circuit to model and analyze the generation of these
sideband noise tones is proposed
- …