An all-digital ΣΔ--frequency discriminator of arbitrary order

In this paper, we propose an all-digital frequency synthesizer architecture, based on an all-digital ΣΔ-frequency discriminator. The new all-digital synthesizer is compared to previously published work. The architecture of the ΣΔ-frequency discriminator is verified using behavioral simulation

Design and analysis of optimized CORDIC based GMSK system on FPGA platform

The Gaussian minimum shift keying (GMSK) is one of the best suited digital modulation schemes in the global system for mobile communication (GSM) because of its constant envelop and spectral efficiency characteristics. Most of the conventional GMSK approaches failed to balance the digital modulation with efficient usage of spectrum. In this article, the hardware architecture of the optimized CORDIC-based GMSK system is designed, which includes GMSK Modulation with the channel and GMSK Demodulation. The modulation consists of non-return zero (NRZ) encoder, an integrator followed by Gaussian filtering and frequency modulation (FM). The GMSK demodulation consists of FM demodulator, followed by differentiation and NRZ decoder. The FM Modulation and demodulation use the optimized CORDIC model for an In-phase (I) and quadrature (Q) phase generation. The optimized CORDIC is designed by using quadrant mapping and pipelined structure to improve the hardware and computational complexity in GMSK systems. The GMSK system is designed on the Xilinx platform and implemented on Artix-7 and Spartan-3EFPGA. The hardware constraints like area, power, and timing utilization are summarized. The comparison of the optimized CORDIC model with similar CORDIC approaches is tabulated with improvements

Low-to-Medium Power Single Chip Digital Controlled DC-DC Regulator for Point-of-Load Applications

A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal

Fractional-N Synthesizer Architectures with Digital Phase Detection.

During the last decade there has been unprecedented growth in the use of portable wireless communications devices for applications as diverse as medical implants, industrial inventory control, and consumer electronics. If these communication devices are to be low power, flexible, and reconfigurable, new radio architectures are needed which take advantage of the major strength of state-of-the-art digital manufacturing processes; that is the ability to build large, complex low power signal processing circuits, with extremely fast clocking speeds. However, traditional radio architectures rely on analog techniques which are ill suited for the use in modern highly integrated digital systems. A critical component of a radio system is the frequency synthesizer, a circuit which can accurately synthesize and modulate high frequency signals. Traditional synthesizers still utilize a significant amount of analog circuitry. In this work, techniques are developed to replace this analog circuitry with digital equivalents. To do this, a digital phase detection scheme for a Fractional-N Phase Lock Loop (FPLL) is presented. The all-digital phase detector can be used as an alternative to a conventional analog-intensive phase detector, charge pump and loop filter blocks. Another limitation of traditional synthesizers is the difficulty in modulating the frequency of the output signal at speeds larger the FPLL’s bandwidth. A new technique is developed for modulating the output frequency of the FPLL at rates significantly faster than the loop bandwidth would typically allow. A digital sampling scheme that enables FSK modulation rates much larger than the loop bandwidth is demonstrated. The new scheme does not compromise on the frequency accuracy of the output signal. The key ideas presented have been proven in a proof of concept design. A prototype 2.2GHz fractional-N synthesizer, incorporating the digital phase detector and sampling scheme is presented as a proof of concept. Although the loop bandwidth is only 142kHz, an FSK modulation rate of 927.5kbs is achieved. The prototype is implemented in 0.13μm CMOS and consumes 14mW from a 1.4V supply.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/60888/1/mferriss_1.pd

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

External Cavity Mode-locked Semiconductor Lasers For The Generation Of Ultra-low Noise Multi-gigahertz Frequency Combs And Applications In Multi-heterodyne Detection Of Arbitrary Optical Waveforms

The construction and characterization of ultra-low noise semiconductor-based mode-locked lasers as frequency comb sources with multi-gigahertz combline-to-combline spacing is studied in this dissertation. Several different systems were built and characterized. The first of these systems includes a novel mode-locking mechanism based on phase modulation and periodic spectral filtering. This mode-locked laser design uses the same intra-cavity elements for both mode-locking and frequency stabilization to an intra-cavity, 1,000 Finesse, Fabry-Pérot Etalon (FPE). On a separate effort, a mode-locked laser based on a Slab-Coupled Optical Waveguide Amplifier (SCOWA) was built. This system generates a pulse-train with residual timing jitter o