14 research outputs found
Direct Conversion RF Front-End Implementation for Ultra-Wideband (UWB) and GSM/WCDMA Dual-Band Applications in Silicon-Based Technologies
This dissertation focuses on wideband circuit design and implementation issues up to 10GHz based on the direct conversion architecture in the CMOS and SiGe BiCMOS technologies. The dissertation consists of two parts: One, implementation of a RF front-end receiver for an ultra-wideband system and, two, implementation of a local oscillation (LO) signal for a GSM/WCDMA multiband application. For emerging ultra-wideband (UWB) applications, the key active components in the RF front-end receiver were designed and implemented in 0.18um SiGe BiCMOS process. The design of LNA, which is the critical circuit block for both systems, was analyzed in terms of noise, linearity and group delay variation over an extemely wide bandwidth. Measurements are demonstrated for an energy-thrifty UWB receiver based on an MB-OFDM system covering the full FCC-allowed UWB frequency range.
For multiband applications such as a GSM/WCDMA dual-band application, the design of wideband VCO and various frequency generation blocks are investigated as alternatives for implementation of direct conversion architecture. In order to reduce DC-offset and LO pulling phenomena that degrade performance in a typical direct conversion scheme, an innovative fractional LO signal generator was implemented in a standard CMOS process. A simple analysis is provided for the loop dynamics and operating range of the design as well as for the measured results of the factional LO signal generator.Ph.D.Committee Chair: Dr. Laskar, Joy; Committee Member: Dr. Cressler, John; Committee Member: Dr. Kohl, Paul; Committee Member: Dr. Papapolymerou, John; Committee Member: Dr. Scott, Waymon
Continuous-time low-pass filters for integrated wideband radio receivers
This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work.
After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations.
Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-µm SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-µm and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented
High frequency of low noise amplifier architecture for WiMAX application: A review
The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure
Design of a 3.1-4.8 GHZ RF front-end for an ultra wideband receiver
IEEE 802.15 High Rate Alternative PHY task group (TG3a) is working to define
a protocol for Wireless Personal Area Networks (WPANs) which makes it possible to
attain data rates of greater than 110Mbps. Ultra Wideband (UWB) technology utilizing
frequency band of 3.168 GHz 10.6 GHz is an emerging solution to this with data rates
of 110, 200 and 480 Mbps. Initially, UWB mode I devices using only 3.168 GHz 4.752
GHz have been proposed.
Low Noise Amplifier (LNA) and I-Q mixers are key components constituting the
RF front-end. Performance of these blocks is very critical to the overall performance of
the receiver. In general, main considerations for the LNA are low noise, 50 broadband
input matching, high gain with maximum flatness and good linearity. For the mixers, it
is essential to attain low flicker noise performance coupled with good conversion gain.
Proposed LNA architecture is a derivative of inductive source degenerated topology.
Broadband matching at the LNA output is achieved using LC band-pass filter. To obtain
high gain with maximum flatness, an LC band-pass filter is used at its output. Proposed
LNA achieved a gain of 15dB, noise figure of less than 2.6dB and IIP3 of more than
-7dBm.
Mixer is a modified version of double balanced Gilbert cell topology where both
I and Q channel mixers are merged together. Frequency response of each sub-band is
matched by using an additional inductor, which further improves the noise figure and
conversion gain. Current bleeding scheme is used to further reduce the low frequency
noise. Mixer achieves average conversion gain of 14.5dB, IIP3 more than 6dBm and
Double Side Band (DSB) noise figure less than 9dB. Maximum variation in conversion
gain is desired to be less than 1dB. Both LNA and mixers are designed to be fabricated
in TSMC 0.18µm CMOS technology
Dual-band FSK receiver and building block design for UWB impulse radio
Master'sMASTER OF ENGINEERIN
CMOS radio frequency circuits for short-range direct-conversion receivers
The research described in this thesis is focused on the design and implementation of radio frequency (RF) circuits for direct-conversion receivers. The main interest is in RF front-end circuits, which contain low-noise amplifiers, downconversion mixers, and quadrature local oscillator signal generation circuits. Three RF front-end circuits were fabricated in a short-channel CMOS process and experimental results are presented.
A low-noise amplifier (LNA) is typically the first amplifying block in the receiver. A large number of LNAs have been reported in the literature. In this thesis, wideband LNA structures are of particular interest. The most common and relevant LNA topologies are analyzed in detail in the frequency domain and theoretical limitations are found. New LNA structures are presented and a comparison to the ones found in the literature is made. In this work, LNAs are implemented with downconversion mixers as RF front-ends. The designed mixers are based on the commonly used Gilbert cell. Different mixer implementation alternatives are presented and the design of the interface between the LNA and the downconversion mixer is discussed.
In this work, the quadrature local oscillator signal is generated either by using frequency dividers or polyphase filters (PPF). Different possibilities for implementing frequency dividers are briefly described. Polyphase filters were already introduced by the 1970s and integrated circuit (IC) realizations to generate quadrature signals have been published since the mid-1990s. Although several publications where the performance of the PPFs has been studied either by theoretical calculations or simulations can be found in the literature, none of them covers all the relevant design parameters. In this thesis, the theory behind the PPFs is developed such that all the relevant design parameters needed in the practical circuit design have been calculated and presented with closed-form equations whenever possible. Although the main focus was on twoand three-stage PPFs, which are the most common ones encountered in practical ICs, the presented calculation methods can be extended to analyze the performance of multistage PPFs as well.
The main application targets of the circuits presented in this thesis are the short-range wireless sensor system and ultrawideband (UWB). Sensors are capable of monitoring temperature, pressure, humidity, or acceleration, for example. The amount of transferred data is typically small and therefore a modest bit rate, less than 1 Mbps, is adequate. The sensor system applied in this thesis operates at 2.4-GHz ISM band (Industrial, Scientific, and Medical). Since the sensors must be able to operate independently for several years, extremely low power consumption is required. In sensor radios, the receiver current consumption is dominated by the blocks and elements operating at the RF. Therefore, the target was to develop circuits that can offer satisfactory performance with a current consumption level that is small compared to other receivers targeted for common cellular systems.
On the other hand, there is a growing need for applications that can offer an extremely high data rate. UWB is one example of such a system. At the moment, it can offer data rates of up to 480 Mbps. There is a frequency spectrum allocated for UWB systems between 3.1 and 10.6 GHz. The UWB band is further divided into several narrower band groups (BG), each occupying a bandwidth of approximately 1.6 GHz. In this work, a direct-conversion RF front-end is designed for a dual-band UWB receiver, which operates in band groups BG1 and BG3, i.e. at 3.1 – 4.8 GHz and 6.3 – 7.9 GHz frequency areas, respectively. Clearly, an extremely wide bandwidth combined with a high operational frequency poses challenges for circuit design. The operational bandwidths and the interfaces between the circuit blocks need to be optimized to cover the wanted frequency areas. In addition, the wideband functionality should be achieved without using a number of on-chip inductors in order to minimize the die area, and yet the power consumption should be kept as small as possible.
The characteristics of the two main target applications are quite different from each other with regard to power consumption, bandwidth, and operational frequency requirements. A common factor for both is their short, i.e. less than 10 meters, range. Although the circuits presented in this thesis are targeted on the two main applications mentioned above, they can be utilized in other kind of wireless communication systems as well. The performance of three experimental circuits was verified with measurements and the results are presented in this work. Two of them have been a part of a whole receiver including baseband amplifiers and filters and analog-to-digital converters. Experimental circuits were fabricated in a 0.13-µm CMOS process. In addition, this thesis includes design examples where new circuit ideas and implementation possibilities are introduced by using 0.13-µm and 65-nm CMOS processes. Furthermore, part of the theory presented in this thesis is validated with design examples in which actual IC component models are used.Tässä väitöskirjassa esitetty tutkimus keskittyy suoramuunnosvastaanottimen radiotaajuudella (radio frequency, RF) toimivien piirien suunnitteluun ja toteuttamiseen. Työ keskittyy vähäkohinaiseen vahvistimeen (low-noise amplifier, LNA), alassekoittajaan ja kvadratuurisen paikallisoskillaattorisignaalin tuottavaan piiriin. Työssä toteutettiin kolme RF-etupäätä erittäin kapean viivanleveyden CMOS-prosessilla, ja niiden kokeelliset tulokset esitetään.
Vähäkohinainen vahvistin on yleensä ensimmäinen vahvistava lohko vastaanottimessa. Useita erilaisia vähäkohinaisia vahvistimia on esitetty kirjallisuudessa. Tämän työn kohteena ovat eritoten laajakaistaiset LNA-rakenteet. Tässä työssä analysoidaan taajuustasossa yleisimmät ja oleellisimmat LNA-topologiat. Lisäksi uusia LNA-rakenteita on esitetty tässä työssä ja niitä on verrattu muihin kirjallisuudessa esitettyihin piireihin. Tässä työssä LNA:t on toteutettu yhdessä alassekoittimen kanssa muodostaen RF-etupään. Työssä suunnitellut alassekoittimet perustuvat yleisesti käytettyyn Gilbertin soluun. Erilaisia sekoittajan suunnitteluvaihtoehtoja ja LNA:n ja alassekoittimen välisen rajapinnan toteutustapoja on esitetty.
Tässä työssä kvadratuurinen paikallisoskillaattorisignaali on muodostettu joko käyttämällä taajuusjakajia tai monivaihesuodattimia. Erilaisia taajuusjakajia ja niiden toteutustapoja käsitellään yleisellä tasolla. Monivaihesuodatinta, joka on alunperin kehitetty jo 1970-luvulla, on käytetty integroiduissa piireissä kvadratuurisignaalin tuottamiseen 1990-luvun puolivälistä lähtien. Kirjallisuudesta löytyy lukuisia artikkeleita, joissa monivaihesuodattimen toimintaa on käsitelty teoreettisesti laskien ja simuloinnein. Kuitenkaan kaikkia sen suunnitteluparametreja ei tähän mennessä ole käsitelty. Tässä työssä monivaihesuodattimen teoriaa on kehitetty edelleen siten, että käytännön piirisuunnittelussa tarvittavat oleelliset parametrit on analysoitu ja suunnitteluyhtälöt on esitetty suljetussa muodossa aina kuin mahdollista. Vaikka työssä on keskitytty yleisimpiin eli kaksi- ja kolmiasteisiin monivaihesuodattimiin, on työssä esitetty menetelmät, joilla laskentaa voidaan jatkaa aina useampiasteisiin suodattimiin asti.
Työssä esiteltyjen piirien pääkohteina ovat lyhyen kantaman sensoriradio ja erittäin laajakaistainen järjestelmä (ultrawideband, UWB). Sensoreilla voidaan tarkkailla esimerkiksi ympäristön lämpötilaa, kosteutta, painetta tai kiihtyvyyttä. Siirrettävän tiedon määrä on tyypillisesti vähäistä, jolloin pieni tiedonsiirtonopeus, alle 1 megabitti sekunnissa, on välttävä. Tämän työn kohteena oleva sensoriradiojärjestelmä toimii kapealla kaistalla 2,4 gigahertsin ISM-taajuusalueella (Industrial, Scientific, and Medical). Koska sensorien tavoitteena on toimia itsenäisesti ilman pariston vaihtoa useita vuosia, täytyy niiden kuluttaman virran olla erittäin vähäistä. Sensoriradiossa vastaanottimen tehonkulutuksen kannalta määräävässä asemassa ovat radiotaajuudella toimivat piirit. Tavoitteena oli tutkia ja kehittää piirirakenteita, joilla päästään tyydyttävään suorituskykyyn tehonkulutuksella, joka on vähäinen verrattuna muiden tavallisten langattomien tiedonsiirtojärjestelmien radiovastaanottimiin.
Toisaalta viime aikoina on kasvanut tarvetta myös järjestelmille, jotka kykenevät tarjoamaan erittäin korkean tiedonsiirtonopeuden. UWB on esimerkki tällaisesta järjestelmästä. Tällä hetkellä se tarjoaa tiedonsiirtonopeuksia aina 480 megabittiin sekunnissa. UWB:lle on varattu taajuusalueita 3,1 ja 10,6 gigahertsin taajuuksien välillä. Kyseinen kaista on edelleen jaettu pienempiin taajuusryhmiin (band group, BG), joiden kaistanleveys on noin 1,6 gigahertsiä. Tässä työssä on toteutettu RF-etupää radiovastaanottimeen, joka pystyy toimimaan BG1:llä ja BG3:lla eli taajuusalueilla 3,1 - 4,7 GHz ja 6,3 - 7,9 GHz. Erittäin suuri kaistanleveys yhdistettynä korkeaan toimintataajuuteen tekee radiotaajuuspiirien suunnittelusta haasteellista. Piirirakenteiden toimintakaistat ja piirien väliset rajapinnat tulee optimoida riittävän laajoiksi käyttämättä kuitenkaan liian montaa piille integroitua kelaa piirin pinta-alan minimoimiseksi, ja lisäksi piirit tulisi toteuttaa mahdollisimman alhaisella tehonkulutuksella.
Työssä esiteltyjen piirien kaksi pääkohdetta ovat hyvin erityyppisiä, mitä tulee tehonkulutus-, kaistanleveys- ja toimintataajuusvaatimuksiin. Yhteistä molemmille on lyhyt, alle 10 metrin kantama. Vaikka tässä työssä esitellyt piirit onkin kohdennettu kahteen pääsovelluskohteeseen, voidaan esitettyjä piirejä käyttää myös muiden tiedonsiirtojärjestelmien piirien suunnitteluun. Tässä työssä esitetään mittaustuloksineen yhteensä kolme kokeellista piiriä yllämainittuihin järjestelmiin. Kaksi ensimmäistä kokeellista piiriä muodostaa kokonaisen radiovastaanottimen yhdessä analogisten kantataajuusosien ja analogia-digitaali-muuntimien kanssa. Esitetyt kokeelliset piirit on toteutettu käyttäen 0,13 µm:n viivanleveyden CMOS-tekniikkaa. Näiden lisäksi työ pitää sisällään piirisuunnitteluesimerkkejä, joissa esitetään ideoita ja mahdollisuuksia käyttäen 0,13 µm:n ja 65 nm:n viivanleveyden omaavia CMOS-tekniikoita. Lisäksi piirisuunnitteluesimerkein havainnollistetaan työssä esitetyn teorian paikkansapitävyyttä käyttämällä oikeita komponenttimalleja.reviewe
High performance building blocks for wireless receiver: multi-stage amplifiers and low noise amplifiers
Different wireless communication systems utilizing different standards and for multiple
applications have penetrated the normal people's life, such as Cell phone, Wireless LAN,
Bluetooth, Ultra wideband (UWB) and WiMAX systems. The wireless receiver normally
serves as the primary part of the system, which heavily influences the system performance.
This research concentrates on the designs of several important blocks of the receiver;
multi-stage amplifier and low noise amplifier.
Two novel multi-stage amplifier typologies are proposed to improve the bandwidth and
reduce the silicon area for the application where a large capacitive load exists. They were
designed using AMI 0.5 m µ CMOS technology. The simulation and measurement results
show they have the best Figure-of-Merits (FOMs) in terms of small signal and large signal
performances, with 4.6MHz and 9MHz bandwidth while consuming 0.38mW and 0.4mW
power from a 2V power supply. Two Low Noise Amplifiers (LNAs) are proposed, with one designed for narrowband
application and the other for UWB application. A noise reduction technique is proposed for
the differential cascode Common Source LNA (CS-LNA), which reduces the LNA Noise
Figure (NF), increases the LNA gain, and improves the LNA linearity. At the same time, a
novel Common Gate LNA (CG-LNA) is proposed for UWB application, which has better
linearity, lower power consumption, and reasonable noise performance.
Finally a novel practical current injection built-in-test (BIT) technique is proposed for the
RF Front-end circuits. If the off-chip component Lg and Rs values are well controlled, the
proposed technique can estimate the voltage gain of the LNA with less than 1dB (8%) error