Analog and Neuromorphic computing with a framework on a reconfigurable platform

The objective of the research is to demonstrate energy-efficient computing on a configurable platform, the Field Programmable Analog Array (FPAA), by leveraging analog strengths, along with a framework, to enable real-time systems on hardware. By taking inspiration from biology, fundamental blocks of neurons and synapses are built, understanding the computational advantages of such neural structures. To enable this computation and scale up from these modules, it is important to have an infrastructure that adapts by taking care of non-ideal effects like mismatches and variations, which commonly plague analog implementations. Programmability, through the presence of floating gates, helps to reduce these variations, thereby ultimately paving the path to take physical approaches to build larger systems in a holistic manner.Ph.D

Mixed signal VLSI circuit implementation of the cortical microcircuit models

This thesis proposes a novel set of generic and compact biologically plausible VLSI (Very Large Scale Integration) neural circuits, suitable for implementing a parallel VLSI network that closely resembles the function of a small-scale neocortical network. The proposed circuits include a cortical neuron, two different long-term plastic synapses and four different short-term plastic synapses. These circuits operate in accelerated-time, where the time scale of neural responses is approximately three to four orders of magnitude faster than the biological-time scale of the neuronal activities, providing higher computational throughput in computing neural dynamics. Further, a novel biological-time cortical neuron circuit with similar dynamics as of the accelerated-time neuron is proposed to demonstrate the feasibility of migrating accelerated-time circuits into biological-time circuits. The fabricated accelerated-time VLSI neuron circuit is capable of replicating distinct firing patterns such as regular spiking, fast spiking, chattering and intrinsic bursting, by tuning two external voltages. It reproduces biologically plausible action potentials. This neuron circuit is compact and enables implementation of many neurons in a single silicon chip. The circuit consumes extremely low energy per spike (8pJ). Incorporating this neuron circuit in a neural network facilitates diverse non-linear neuron responses, which is an important aspect in neural processing. Two of the proposed long term plastic synapse circuits include spike-time dependent plasticity (STDP) synapse, and dopamine modulated STDP synapse. The short-term plastic synapses include excitatory depressing, inhibitory facilitating, inhibitory depressing, and excitatory facilitating synapses. Many neural parameters of short- and long- term synapses can be modified independently using externally controlled tuning voltages to obtain distinct synaptic properties. Having diverse synaptic dynamics in a network facilitates richer network behaviours such as learning, memory, stability and dynamic gain control, inherent in a biological neural network. To prove the concept in VLSI, different combinations of these accelerated-time neural circuits are fabricated in three integrated circuits (ICs) using a standard 0.35 µm CMOS technology. Using first two ICs, functions of cortical neuron and STDP synapses have been experimentally verified. The third IC, the Cortical Neural Layer (CNL) Chip is designed and fabricated to facilitate cortical network emulations. This IC implements neural circuits with a similar composition to the cortical layer of the neocortex. The CNL chip comprises 120 cortical neurons and 7 560 synapses. Many of these CNL chips can be combined together to form a six-layered VLSI neocortical network to validate the network dynamics and to perform neural processing of small-scale cortical networks. The proposed neuromorphic systems can be used as a simulation acceleration platform to explore the processing principles of biological brains and also move towards realising low power, real-time intelligent computing devices and control systems.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Mixed signal VLSI circuit implementation of the cortical microcircuit models

This thesis proposes a novel set of generic and compact biologically plausible VLSI (Very Large Scale Integration) neural circuits, suitable for implementing a parallel VLSI network that closely resembles the function of a small-scale neocortical network. The proposed circuits include a cortical neuron, two different long-term plastic synapses and four different short-term plastic synapses. These circuits operate in accelerated-time, where the time scale of neural responses is approximately three to four orders of magnitude faster than the biological-time scale of the neuronal activities, providing higher computational throughput in computing neural dynamics. Further, a novel biological-time cortical neuron circuit with similar dynamics as of the accelerated-time neuron is proposed to demonstrate the feasibility of migrating accelerated-time circuits into biological-time circuits. The fabricated accelerated-time VLSI neuron circuit is capable of replicating distinct firing patterns such as regular spiking, fast spiking, chattering and intrinsic bursting, by tuning two external voltages. It reproduces biologically plausible action potentials. This neuron circuit is compact and enables implementation of many neurons in a single silicon chip. The circuit consumes extremely low energy per spike (8pJ). Incorporating this neuron circuit in a neural network facilitates diverse non-linear neuron responses, which is an important aspect in neural processing. Two of the proposed long term plastic synapse circuits include spike-time dependent plasticity (STDP) synapse, and dopamine modulated STDP synapse. The short-term plastic synapses include excitatory depressing, inhibitory facilitating, inhibitory depressing, and excitatory facilitating synapses. Many neural parameters of short- and long- term synapses can be modified independently using externally controlled tuning voltages to obtain distinct synaptic properties. Having diverse synaptic dynamics in a network facilitates richer network behaviours such as learning, memory, stability and dynamic gain control, inherent in a biological neural network. To prove the concept in VLSI, different combinations of these accelerated-time neural circuits are fabricated in three integrated circuits (ICs) using a standard 0.35 µm CMOS technology. Using first two ICs, functions of cortical neuron and STDP synapses have been experimentally verified. The third IC, the Cortical Neural Layer (CNL) Chip is designed and fabricated to facilitate cortical network emulations. This IC implements neural circuits with a similar composition to the cortical layer of the neocortex. The CNL chip comprises 120 cortical neurons and 7 560 synapses. Many of these CNL chips can be combined together to form a six-layered VLSI neocortical network to validate the network dynamics and to perform neural processing of small-scale cortical networks. The proposed neuromorphic systems can be used as a simulation acceleration platform to explore the processing principles of biological brains and also move towards realising low power, real-time intelligent computing devices and control systems.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Fabrication and Application of a Polymer Neuromorphic Circuitry Based on Polymer Memristive Devices and Polymer Transistors

Neuromorphic engineering is a discipline that aims to address the shortcomings of today\u27s serial computers, namely large power consumption, susceptibility to physical damage, as well as the need for explicit programming, by applying biologically-inspired principles to develop neural systems with applications such as machine learning and perception, autonomous robotics and generic artificial intelligence. This doctoral dissertation presents work performed fabricating a previously developed type of polymer neuromorphic architecture, termed Polymer Neuromorphic Circuitry (PNC), inspired by the McCulloch-Pitts model of an artificial neuron. The major contribution of this dissertation is a development of processing techniques necessary to realize the Polymer Neuromorphic Circuitry, which required a development of individual polymer electronics elements, as well as customization of fabrication processes necessary for the realization of the circuitry on separate substrates as well as on a single substrate. This is the first demonstration of a fabrication of an entire neuron, and more importantly, a network of such neurons, that includes both the weighting functionality of a synapse and the somatic summing, all realized with polymer electronics technology. Polymer electronics is a new branch of electronics that is based on conductive and semi-conductive polymers. These new elements hold a great advantage over the conventional, inorganic electronics in the form of physical flexibility, low cost and ease of fabrication, manufacturing compatibility with many substrate materials, as well as greater biological compatibility. These advantages were the primary motivation for the choice to fabricate all of the electrical components required to realize the PNC, namely polymer transistors, polymer memristive devices, and polymer resistors, with polymer electronics components. The efficacy of this design is validated by demonstrating that the activation function of a single neuron approximates the sigmoidal function commonly employed by artificial neural networks. The utility of the neuromorphic circuitry is further corroborated by illustrating that a network of such neurons, and even a single neuron, are capable of performing linear classification for a real-life problem

Open collaborative system design : a strategic framework with application to synthetic biology

Thesis (Ph. D.)--Massachusetts Institute of Technology, Engineering Systems Division, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 251-259).Across technology industries and particularly at the cutting edge of biotechnology a debate is under way about the proper balance between open and closed - between co-developing products with shared information and open standards, versus using more traditional, closed, proprietary processes. Beyond the relative success of open source software to date, it is not clear how and whether open design processes might be applied generally for complex, assembled technologies. This problem takes on special urgency within the domain of synthetic biology, an emerging discipline in which many practitioners advocate opening design and development through platforms such as the registry of standardized biological parts. Biotechnology is IP intensive in part because commercialization is complicated and capital intensive. How might one develop a sustainable open development process in this context? This thesis addresses these questions from an Engineering Systems perspective. Defining open, collaborative system development (OCSD) specifically as a process in which subsystems are created voluntarily by an unrestricted set of third-party contributors, it makes the following claim: An OCSD process can itself be designed, with the principal objective of creating an environment for third-party innovation. To support this claim the thesis outlines a conceptual framework to guide OCSD design. The framework includes a taxonomy of parameters and constraints relevant to opening design, a list of options within each taxonomic category, and three high level strategies found to recur as a function of sponsor goals and technological constraints. Finally, the thesis proposes a quantitative method, based on multidisciplinary modeling and pareto analysis, to design open standards within the context of one of the three strategies. The research is carried out through a pragmatic blend of case studies and quantitative modeling. First, an in-depth, multi-discipline literature review synthesizes relevant taxonomic categories. Thirteen examples of OCSD spanning nine industries are then analyzed to define options within each taxonomic category. The case studies are also used to identify strategies for opening design based on correlations between OCSD options. The framework is validated and expanded through an in-depth case study of the opening of Very Large Scale Integration (VLSI) in the semi-conductor industry in the late 1970s. Finally, a quantitative method is developed to guide the design of open standards within one of the three strategies. These three contributions - the framework, correlated strategies, and quantitative method - are then applied to a particular biotechnology called microbial fuel cells.by Matthew Robin Silver.Ph.D

NASA Tech Briefs, June 1996

Topics: New Computer Hardware; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences;Books and Reports

A Solder-Defined Computer Architecture for Backdoor and Malware Resistance

This research is about securing control of those devices we most depend on for integrity and confidentiality. An emerging concern is that complex integrated circuits may be subject to exploitable defects or backdoors, and measures for inspection and audit of these chips are neither supported nor scalable. One approach for providing a “supply chain firewall” may be to forgo such components, and instead to build central processing units (CPUs) and other complex logic from simple, generic parts. This work investigates the capability and speed ceiling when open-source hardware methodologies are fused with maker-scale assembly tools and visible-scale final inspection. The author has designed, and demonstrated in simulation, a 36-bit CPU and protected memory subsystem that use only synchronous static random access memory (SRAM) and trivial glue logic integrated circuits as components. The design presently lacks preemptive multitasking, ability to load firmware into the SRAMs used as logic elements, and input/output. Strategies are presented for adding these missing subsystems, again using only SRAM and trivial glue logic. A load-store architecture is employed with four clock cycles per instruction. Simulations indicate that a clock speed of at least 64 MHz is probable, corresponding to 16 million instructions per second (16 MIPS), despite the architecture containing no microprocessors, field programmable gate arrays, programmable logic devices, application specific integrated circuits, or other purchased complex logic. The lower speed, larger size, higher power consumption, and higher cost of an “SRAM minicomputer,” compared to traditional microcontrollers, may be offset by the fully open architecture—hardware and firmware—along with more rigorous user control, reliability, transparency, and auditability of the system. SRAM logic is also particularly well suited for building arithmetic logic units, and can implement complex operations such as population count, a hash function for associative arrays, or a pseudorandom number generator with good statistical properties in as few as eight clock cycles per 36-bit word processed. 36-bit unsigned multiplication can be implemented in software in 47 instructions or fewer (188 clock cycles). A general theory is developed for fast SRAM parallel multipliers should they be needed

Approche hybride : une approche pour une meilleure intégration des outils CAAD dans le développement du processus architecturale du projet

Avec l’usage élargi de la CAAO, ces outils ont été largement utilisés dans le processus de conception architecturale. En dépit des fonctionnalités avancées offertes par les systèmes de CAAO, l'utilisation de la CAAO est principalement concentrée dans les étapes de production, comme un support graphique pour le dessin, la modélisation, le rendu et la simulation. Par conséquent, il est raisonnable de considérer que la situation actuelle relative à l’usage de la CAAO dans la profession d'architecte appelle à de nouvelles améliorations. En d'autres termes, nous devons trouver un moyen de mieux intégrer la technologie et les outils de CAAO dans le processus de conception architecturale, qui est notre question de recherche. Nous avons besoin de savoir comment la CAAO pourrait être utilisée pour améliorer la capacité de conception de l'architecte. Il ressort des discussions et des recherches menées pour cette étude que nous voulons un soutien de la technologie pour nous aider à mieux concevoir et non pas que la technologie conçoive à notre place. Nous aimerions avoir un système de CAAO qui pourrait nous servir d’assistant à la conception. En étudiant la situation de l'intégration des outils de CAAO dans les pratiques actuelles de conception des architectes et en examinant les approches utilisées dans les premières tentatives de développement d’un outil de CAAO intégré au processus de conception, on peut conclure que l'approche exploratoire et heuristique serait une meilleure approche qui pourrait être adaptée pour développer un système CAAO en soutien au travail de l’architecte. De plus, une étude plus approfondie a démontré que les deux sous- approches des approches exploratoires et heuristiques (approches basées sur les cas et les contraintes), sont applicables, mais aucune d'elles n'est suffisante. Par conséquent, l’approche hybride qui prend en compte les avantages de chacune des deux sous- approches précitées serait la plus applicable. Elle nous permettrait de développer un outil CAAD qui pourrait vraiment être intégré dans le processus de conception architecturale. Cette conclusion a été vérifiée par une étude complémentaire basée sur des entrevues.The CAAD tools have been widely adopted in the architectural design process with the popular utilization of CAAD. In spite of the advanced features that have been designed for the CAAD systems, the utilization of CAAD is mainly concentrated on the production stage of design, as a graphic medium for drawing, modeling, rendering and simulation. Therefore, it is reasonable to deem that the current situation of CAAD tools involvement in the architectural profession is calling for further improvement. In other words, we need to find a way to better integrate the CAAD tools/technology into the architectural conceptual design stage, which is our research question. We need to find out how CAAD could be utilized to improve the architect’s design ability during the conceptual design. The discussion and research conducted for this study lead to the assessment that we want technology to help us design better, but not to design for us. We would like to have a CAAD system that could help us as a design assistant. By studying the current situation of the integration of CAAD tools into architects’ design practice and reviewing the approaches that have been employed to create a CAAD tool that could be better integrated into the design process, we reach the decision that the exploring & heuristic approach would be a preferred approach that could be adopted to further develop a more feasible CAAD system. In addition, within the two sub-approaches of the Exploring & Heuristic Approaches (case-based approach and constraint approach), further study has proved that both of them are applicable approaches, but neither of them could sufficiently serve as the sole approach for this purpose. Therefore, a hybrid approach that takes advantage of both approaches would be the most applicable one because it can help us develop a CAAD tool that could be really integrated into the conceptual architectural design procedure