Design of bias circuit for charge pump in 130nm BiCMOS technology

El presente trabajo muestra el diseño de un circuito de polarización en la tecnología de 130nm BiCMOS con las herramientas de diseño de Cadence. El circuito de polarización es parte de un circuito Charge Pump (CP), el cual a su vez es parte de un circuito PLL (Phased Locked Loop) que se utilizará en una implementación de señal mixta de un Recuperador de Datos (CDR). Al inicio del trabajo se presenta una descripción general de los módulos analógicos y digitales que conforman el proyecto. La topología de diseño propuesta refleja la enorme dependencia del circuito de polarización con el circuito CP. Un circuito replica permite “seguir” las variaciones de carga y descarga de corriente del circuito CP para compensar mediante un OTA (Operational Transconductance Amplifier) el nivel de voltaje requerido en los transistores del circuito diferencial del CP. El proceso de diseño, la generación de esquemáticos y bancos de pruebas son mostrados durante los primeros capítulos del trabajo. La verificación del diseño pre-layout a través del proceso de esquinas, así como el uso el uso de las herramientas de verificación de reglas de diseño post-layout son mostradas durante los capítulos finales.The present work shows the design of a Bias circuit in 130 nm of BiCMOS process using Cadence tools. The Bias circuit is part of a Charge Pump (CP) circuit, which in turn is one block of a PLL (Phased Locked Loop) that will be used in a mixed-signal implementation of a Clock and Data Recovery (CDR) circuit. This PLL-based CDR is the project of the generation 2018 of the Specialty in System on a Chip at ITESO. A general description of the analog and digital modules that make up this project is shown at the beginning of this work. As it is described in detail in this work, the proposed design topology reveals the enormous dependence of the polarization circuit to the CP circuit. The replica method used in the Bias circuit allows to "follow" the current variations of CP charge/discharge process to compensate through an OTA (Operational Transconductance Amplifier) the level of voltage required by the tail transistors of CP circuit. The design procedure, the generation of schematics and test benches are shown during the first chapters of this work. The verification of the pre-layout design through the corners process, as well as the use of the post-layout design rules verification tools, are shown during the final chapters of this work.Consejo Nacional de Ciencia y Tecnologí

High-Speed Low-Power Analog to Digital Converter for Digital Beam Forming Systems

abstract: Time-interleaved analog to digital converters (ADCs) have become critical components in high-speed communication systems. Consumers demands for smaller size, more bandwidth and more features from their communication systems have driven the market to use modern complementary metal-oxide-semiconductor (CMOS) technologies with shorter channel-length transistors and hence a more compact design. Downscaling the supply voltage which is required in submicron technologies benefits digital circuits in terms of power and area. Designing accurate analog circuits, however becomes more challenging due to the less headroom. One way to overcome this problem is to use calibration to compensate for the loss of accuracy in analog circuits. Time-interleaving increases the effective data conversion rate in ADCs while keeping the circuit requirements the same. However, this technique needs special considerations as other design issues associated with using parallel identical channels emerge. The first and the most important is the practical issue of timing mismatch between channels, also called sample-time error, which can directly affect the performance of the ADC. Many techniques have been developed to tackle this issue both in analog and digital domains. Most of these techniques have high complexities especially when the number of channels exceeds 2 and some of them are only valid when input signal is a single tone sinusoidal which limits the application. This dissertation proposes a sample-time error calibration technique which bests the previous techniques in terms of simplicity, and also could be used with arbitrary input signals. A 12-bit 650 MSPS pipeline ADC with 1.5 GHz analog bandwidth for digital beam forming systems is designed in IBM 8HP BiCMOS 130 nm technology. A front-end sample-and-hold amplifier (SHA) was also designed to compare with an SHA-less design in terms of performance, power and area. Simulation results show that the proposed technique is able to improve the SNDR by 20 dB for a mismatch of 50% of the sampling period and up to 29 dB at 37% of the Nyquist frequency. The designed ADC consumes 122 mW in each channel and the clock generation circuit consumes 142 mW. The ADC achieves 68.4 dB SNDR for an input of 61 MHz.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

ON DESIGN OF SELF-TUNING ACTIVE FILTERS

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc

A Versatile Active Block: DXCCCII and Tunable Applications

The study describes dual-X controlled current conveyor (DXCCCII) as a versatile active block and its application to inductance simulators for testing. Moreover, the high pass filter application using with DXCCCII based inductance simulator and oscillator with flexible tunable oscillation frequency have been presented and simulated to confirm the theoretical validity. The proposed circuit which has a simple circuit design requires the low-voltage and the DXCCCII can also be tuned in the wide range by the biasing current. The proposed DXCCCII provides a good linearity, high output impedance at Z terminals, and a reasonable current and voltage transfer gain accuracy. The proposed DXCCCII and its applications have been simulated using the CMOS 0.18 µm technology

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

CMOS ECCCII with Linear Tune of Rx and Its Application to Current-mode Multiplier

In this paper present CMOS second-generation current-controlled-current-conveyor based on differential pair operational transconductance amplifier. Its parasitic resistance at x-port can be linearly controlled by an input bias current. Therefore, a proposed building block is called electronically tunable second-generation current-controlled-current-conveyor (ECCCII). The application presents 2-quadrant and 4-quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program and they are in agreement with the theory

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Current-Controlled Current-Mode Universal Biquad Employing Multi-Output Transconductors

This paper deals with RC active biquad working in the so-called current mode (CM). The design approach uses only three transconductors (OTA) with the minimum necessary number of outputs and with only three passive grounded elements. The proposed filter has simple circuit configuration providing all standard transfer functions such as high-pass (HP), band-pass (BP), low-pass (LP), band-reject (BR) and all-pass (AP). Electronic tuning and independent adjusting of the quality factor and bandwidth of BP filter is possible. The presented circuits are verified by PSpice simulations utilizing OTAs on transistor level of abstraction. The linear parasitic effects of the real active elements in each suggested circuit are briefly discussed. Experimental verification is also given. Designed networks can be used in many applications such as antialiasing filters, in high-speed data telecommunication systems, for signal processing in the cable modems, in regulation and measurement techniques etc