37,136 research outputs found
Design of a ROIC for scanning type HgCdTe LWIR focal plane arrays
Design of a silicon readout integrated circuit (ROIC) for LWIR HgCdTe Focal Plane is presented. ROIC incorporates time delay integration (TDI) functionality over seven elements with a supersampling rate of three, increasing SNR and
the spatial resolution. Novelty of this topology is inside TDI stage; integration of charges in TDI stage implemented in current domain by using switched current structures that reduces required area for chip and improves linearity performance. ROIC, in terms of functionality, is capable of bidirectional scan, programmable integration time and 5 gain settings at the input. Programming can be done parallel or serially with digital interface. ROIC can handle up to 3.5V dynamic range with the input stage to be direct injection (DI) type. With the load being 10pF capacitive in parallel with 1MΩ resistance, output settling time is less than 250nsec enabling the clock frequency up to 4MHz. The manufacturing technology is 0.35μm, double poly-Si, four-metal (3 metals and 1 top metal) 5V CMOS process
Design of a digital compression technique for shuttle television
The determination of the performance and hardware complexity of data compression algorithms applicable to color television signals, were studied to assess the feasibility of digital compression techniques for shuttle communications applications. For return link communications, it is shown that a nonadaptive two dimensional DPCM technique compresses the bandwidth of field-sequential color TV to about 13 MBPS and requires less than 60 watts of secondary power. For forward link communications, a facsimile coding technique is recommended which provides high resolution slow scan television on a 144 KBPS channel. The onboard decoder requires about 19 watts of secondary power
Speculative Segmented Sum for Sparse Matrix-Vector Multiplication on Heterogeneous Processors
Sparse matrix-vector multiplication (SpMV) is a central building block for
scientific software and graph applications. Recently, heterogeneous processors
composed of different types of cores attracted much attention because of their
flexible core configuration and high energy efficiency. In this paper, we
propose a compressed sparse row (CSR) format based SpMV algorithm utilizing
both types of cores in a CPU-GPU heterogeneous processor. We first
speculatively execute segmented sum operations on the GPU part of a
heterogeneous processor and generate a possibly incorrect results. Then the CPU
part of the same chip is triggered to re-arrange the predicted partial sums for
a correct resulting vector. On three heterogeneous processors from Intel, AMD
and nVidia, using 20 sparse matrices as a benchmark suite, the experimental
results show that our method obtains significant performance improvement over
the best existing CSR-based SpMV algorithms. The source code of this work is
downloadable at https://github.com/bhSPARSE/Benchmark_SpMV_using_CSRComment: 22 pages, 8 figures, Published at Parallel Computing (PARCO
VolumeEVM: A new surface/volume integrated model
Volume visualization is a very active research area in the field of scien-tific
visualization. The Extreme Vertices Model (EVM) has proven to be
a complete intermediate model to visualize and manipulate volume data
using a surface rendering approach. However, the ability to integrate the
advantages of surface rendering approach with the superiority in visual exploration
of the volume rendering would actually produce a very complete
visualization and edition system for volume data. Therefore, we decided
to define an enhanced EVM-based model which incorporates the volumetric
information required to achieved a nearly direct volume visualization
technique. Thus, VolumeEVM was designed maintaining the same EVM-based
data structure plus a sorted list of density values corresponding to
the EVM-based VoIs interior voxels. A function which relates interior
voxels of the EVM with the set of densities was mandatory to be defined.
This report presents the definition of this new surface/volume integrated
model based on the well known EVM encoding and propose implementations
of the main software-based direct volume rendering techniques
through the proposed model.Postprint (published version
An ultrahigh-speed digitizer for the Harvard College Observatory astronomical plates
A machine capable of digitizing two 8 inch by 10 inch (203 mm by 254 mm)
glass astrophotographic plates or a single 14 inch by 17 inch (356 mm by 432
mm) plate at a resolution of 11 microns per pixel or 2309 dots per inch (dpi)
in 92 seconds is described. The purpose of the machine is to digitize the
\~500,000 plate collection of the Harvard College Observatory in a five year
time frame. The digitization must meet the requirements for scientific work in
astrometry, photometry, and archival preservation of the plates. This paper
describes the requirements for and the design of the subsystems of the machine
that was developed specifically for this task.Comment: 12 pages, 9 figures, 1 table; presented at SPIE (July, 2006) and
published in Proceeding
Coding and Compression of Three Dimensional Meshes by Planes
The present paper suggests a new approach for geometric representation of 3D
spatial models and provides a new compression algorithm for 3D meshes, which is
based on mathematical theory of convex geometry. In our approach we represent a
3D convex polyhedron by means of planes, containing only its faces. This allows
not to consider topological aspects of the problem (connectivity information
among vertices and edges) since by means of the planes we construct the
polyhedron uniquely. Due to the fact that the topological data is ignored this
representation provides high degree of compression. Also planes based
representation provides a compression of geometrical data because most of the
faces of the polyhedron are not triangles but polygons with more than three
vertices.Comment: 10 pages, 7 figure
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