257 research outputs found

    Design of variability compensation architectures of digital circuits with adaptive body bias

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    The most critical concern in circuit is to achieve high level of performance with very tight power constraint. As the high performance circuits moved beyond 45nm technology one of the major issues is the parameter variation i.e. deviation in process, temperature and voltage (PVT) values from nominal specifications. A key process parameter subject to variation is the transistor threshold voltage (Vth) which impacts two important parameters: frequency and leakage power. Although the degradation can be compensated by the worstcase scenario based over-design approach, it induces remarkable power and performance overhead which is undesirable in tightly constrained designs. Dynamic voltage scaling (DVS) is a more power efficient approach, however its coarse granularity implies difficulty in handling fine grained variations. These factors have contributed to the growing interest in power aware robust circuit design. We propose a variability compensation architecture with adaptive body bias, for low power applications using 28nm FDSOI technology. The basic approach is based on a dynamic prediction and prevention of possible circuit timing errors. In our proposal we are using a Canary logic technique that enables the typical-case design. The body bias generation is based on a DLL type method which uses an external reference generator and voltage controlled delay line (VCDL) to generate the forward body bias (FBB) control signals. The adaptive technique is used for dynamic detection and correction of path failures in digital designs due to PVT variations. Instead of tuning the supply voltage, the key idea of the design approach is to tune the body bias voltage bymonitoring the error rate during operation. The FBB increases operating speed with an overhead in leakage power

    Digital CMOS ISFET architectures and algorithmic methods for point-of-care diagnostics

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    Over the past decade, the surge of infectious diseases outbreaks across the globe is redefining how healthcare is provided and delivered to patients, with a clear trend towards distributed diagnosis at the Point-of-Care (PoC). In this context, Ion-Sensitive Field Effect Transistors (ISFETs) fabricated on standard CMOS technology have emerged as a promising solution to achieve a precise, deliverable and inexpensive platform that could be deployed worldwide to provide a rapid diagnosis of infectious diseases. This thesis presents advancements for the future of ISFET-based PoC diagnostic platforms, proposing and implementing a set of hardware and software methodologies to overcome its main challenges and enhance its sensing capabilities. The first part of this thesis focuses on novel hardware architectures that enable direct integration with computational capabilities while providing pixel programmability and adaptability required to overcome pressing challenges on ISFET-based PoC platforms. This section explores oscillator-based ISFET architectures, a set of sensing front-ends that encodes the chemical information on the duty cycle of a PWM signal. Two initial architectures are proposed and fabricated in AMS 0.35um, confirming multiple degrees of programmability and potential for multi-sensing. One of these architectures is optimised to create a dual-sensing pixel capable of sensing both temperature and chemical information on the same spatial point while modulating this information simultaneously on a single waveform. This dual-sensing capability, verified in silico using TSMC 0.18um process, is vital for DNA-based diagnosis where protocols such as LAMP or PCR require precise thermal control. The COVID-19 pandemic highlighted the need for a deliverable diagnosis that perform nucleic acid amplification tests at the PoC, requiring minimal footprint by integrating sensing and computational capabilities. In response to this challenge, a paradigm shift is proposed, advocating for integrating all elements of the portable diagnostic platform under a single piece of silicon, realising a ``Diagnosis-on-a-Chip". This approach is enabled by a novel Digital ISFET Pixel that integrates both ADC and memory with sensing elements on each pixel, enhancing its parallelism. Furthermore, this architecture removes the need for external instrumentation or memories and facilitates its integration with computational capabilities on-chip, such as the proposed ARM Cortex M3 system. These computational capabilities need to be complemented with software methods that enable sensing enhancement and new applications using ISFET arrays. The second part of this thesis is devoted to these methods. Leveraging the programmability capabilities available on oscillator-based architectures, various digital signal processing algorithms are implemented to overcome the most urgent ISFET non-idealities, such as trapped charge, drift and chemical noise. These methods enable fast trapped charge cancellation and enhanced dynamic range through real-time drift compensation, achieving over 36 hours of continuous monitoring without pixel saturation. Furthermore, the recent development of data-driven models and software methods open a wide range of opportunities for ISFET sensing and beyond. In the last section of this thesis, two examples of these opportunities are explored: the optimisation of image compression algorithms on chemical images generated by an ultra-high frame-rate ISFET array; and a proposed paradigm shift on surface Electromyography (sEMG) signals, moving from data-harvesting to information-focused sensing. These examples represent an initial step forward on a journey towards a new generation of miniaturised, precise and efficient sensors for PoC diagnostics.Open Acces

    Principles of Neuromorphic Photonics

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    In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

    Delay Measurements and Self Characterisation on FPGAs

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    This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure rate and transition probability is proposed for accurate, precise and efficient measurement of propagation delays. The transition probability based method is especially attractive, since it requires no modifications in the circuit-under-test and requires little hardware resources, making it an ideal method for physical delay analysis of FPGA circuits. The relentless advancements in process technology has led to smaller and denser transistors in integrated circuits. While FPGA users benefit from this in terms of increased hardware resources for more complex designs, the actual productivity with FPGA in terms of timing performance (operating frequency, latency and throughput) has lagged behind the potential improvements from the improved technology due to delay variability in FPGA components and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA designs. The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability problem in FPGAs

    Voltage stacking for near/sub-threshold operation

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    Asynchronous techniques for new generation variation-tolerant FPGA

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    PhD ThesisThis thesis presents a practical scenario for asynchronous logic implementation that would benefit the modern Field-Programmable Gate Arrays (FPGAs) technology in improving reliability. A method based on Asynchronously-Assisted Logic (AAL) blocks is proposed here in order to provide the right degree of variation tolerance, preserve as much of the traditional FPGAs structure as possible, and make use of asynchrony only when necessary or beneficial for functionality. The newly proposed AAL introduces extra underlying hard-blocks that support asynchronous interaction only when needed and at minimum overhead. This has the potential to avoid the obstacles to the progress of asynchronous designs, particularly in terms of area and power overheads. The proposed approach provides a solution that is complementary to existing variation tolerance techniques such as the late-binding technique, but improves the reliability of the system as well as reducing the design’s margin headroom when implemented on programmable logic devices (PLDs) or FPGAs. The proposed method suggests the deployment of configurable AAL blocks to reinforce only the variation-critical paths (VCPs) with the help of variation maps, rather than re-mapping and re-routing. The layout level results for this method's worst case increase in the CLB’s overall size only of 6.3%. The proposed strategy retains the structure of the global interconnect resources that occupy the lion’s share of the modern FPGA’s soft fabric, and yet permits the dual-rail iv completion-detection (DR-CD) protocol without the need to globally double the interconnect resources. Simulation results of global and interconnect voltage variations demonstrate the robustness of the method

    Dependable Embedded Systems

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    This Open Access book introduces readers to many new techniques for enhancing and optimizing reliability in embedded systems, which have emerged particularly within the last five years. This book introduces the most prominent reliability concerns from today’s points of view and roughly recapitulates the progress in the community so far. Unlike other books that focus on a single abstraction level such circuit level or system level alone, the focus of this book is to deal with the different reliability challenges across different levels starting from the physical level all the way to the system level (cross-layer approaches). The book aims at demonstrating how new hardware/software co-design solution can be proposed to ef-fectively mitigate reliability degradation such as transistor aging, processor variation, temperature effects, soft errors, etc. Provides readers with latest insights into novel, cross-layer methods and models with respect to dependability of embedded systems; Describes cross-layer approaches that can leverage reliability through techniques that are pro-actively designed with respect to techniques at other layers; Explains run-time adaptation and concepts/means of self-organization, in order to achieve error resiliency in complex, future many core systems

    Adaptive deformable mirror : based on electromagnetic actuators

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    Refractive index variations in the earth's atmosphere cause wavefront aberrations and limit thereby the resolution in ground-based telescopes. With Adaptive Optics (AO) the temporally and spatially varying wavefront distortions can be corrected in real time. Most implementations in a ground based telescope include a WaveFront Sensor, a Deformable Mirror and a real time wavefront control system. The largest optical telescopes built today have a ~ 1 Om primary mirror. Telescopes with more collecting area and higher resolution are desired. ELTs are currently designed with apertures up to 42m. For these telescopes serious challenges for all parts of the AO system exist. This thesis addresses the challenges for the DM. An 8m class telescope on a representative astronomical site is the starting point. The atmosphere is characterized by the spatial and temporal spectra of Kolmogorov turbulence and the frozen flow assumption. The wavefront fitting error, caused by a limited number of actuators and the temporal error, caused by a limited control bandwidth, are the most important for the DM design. It is shown that ~5000 actuators and 200Hz closed loop bandwidth form a balanced choice between the errors and correct an 8m wavefront in the visible to nearly diffraction limited. An actuator stroke of ~5.6J.!m and ~0.36J.!m inter actuator stroke is thereby needed. Together with the nm's resolution, low power dissipation, no hysteresis and drift, these form the main DM requirements. The design, realization and tests of a new DM that meets these requirements and is extendable and scalable in mechanics, electronics and control to suit further Extremely Large Telescopes (ELTs) is presented. In the DM a few layers are distinguished: a continuous mirror facesheet, the actuator grid and the base frame. In the underlying layer - the actuator grid - low voltage electromagnetic push-pull actuators are located. Identical actuator modules, each with 61 actuators, hexagonally arranged on a 6mm pitch can be placed adjacent to form large grids. The base frame provides a stable and stiff reference. A thin facesheet is needed for low actuator forces and power dissipation, whereby its lower limit is set by the facesheets inter actuator deflection determined by gravity or wind pressure. For both scaling laws for force and dissipation are derived. Minimum power dissipation is achieved when beryllium is used for the mirror facesheet. Pyrex facesheets with 100J.!m thickness are chosen as a good practical, alternative in the prototype development. Struts (00.1 x 8mm) connect the facesheet to the actuators and ensure a smooth surface over the imposed heights and allow relative lateral movement of the facesheet and the actuator grid. Measurements show 3nm RMS surface unflattness from the glued attachment. The stiffness of the actuators form the out-of-plane constraints for the mirror facesheet and determine the mirrors first resonance frequency. and is chosen such that the resonance frequency is high enough to allow the high control bandwidth but not higher that needed to avoid excessive power dissipation and fix points in the surface in case of failure. The electromagnetic variable reluctance actuators designed, are efficient, have low moving mass and have suitable stiffness. Other advantages are the low costs, low driving voltages and negligible hysteresis and drift. The actuators consist of a closed magnetic circuit in which a PM provides static magnetic force on a ferromagnetic core that is suspended in a membrane. This attraction force is increased of decreased by a current through a coil. The actuators are free from mechanical hysteresis, friction and play and therefore have a high positioning resolution with high reproducibility. The actuator modules are build in layers to reduces the number of parts and the complexity of assembly and to improve the uniformity in properties. Dedicated communication and driver electronics are designed. FPGA implemented PWM based voltage drivers are chosen because of their high efficiency and capability to be implemented in large numbers with only a few electronic components. A multidrop LVDS based serial communication is chosen for its low power consumption, high bandwidth and consequently low latency, low communication overhead and extensive possibilities for customization. A flat-cable connects up to 32 electronics modules to a custom communications bridge, which translates the ethernet packages from the control PC into LVDS. Two DMs prototypes were successfully assembled: a 050mm DM with 61 actuators and a 0l50mm DM with 427 actuators. In the second prototype modularity is shown by the assembly of seven identical grids on a common base. The dynamic performance of each actuator is measured, including its dedicated driver and communication. All actuators were found to be functional, indicating that the manufacturing and assembly process is reliable. A nonlinear mathematical model of the actuator was derived describing both its static and dynamic behavior based on equations from the magnetic, mechanic and electric domains. The actuator model was linearized, leading to expressions for the actuator transfer function and properties such as motor constant, coil inductance, actuator stiffness and resonance frequency. From frequency response function measurements these properties showed slight deviations from the values derived from the model, but the statistical spread for the properties was small, stressing the reliability of the manufacturing and assembly process. The mean actuator stiffness and resonance frequency were 0.47kN/m and 1.8kHz respectively, which is close to their design values of 500N/m and 1.9kHz. The time domain response of an actuator to a 4Hz sine voltage was used to determine hysteresis and semi-static nonlinear response of the actuator. This showed the first to be negligible and the second to remain below 5% for ±10J.!m stroke. Measurements showed that in the expected operating range, the total power dissipation is dominated by indirect losses in FPGAs. The static DM performance is validated using interferometric measurements. The measured influence matrix is used to shape the mirror facesheet into the first 28 Zernike modes, which includes the piston term that represents the best flat mirror. The total RMS error is ~25nm for all modes. The dynamic behavior of the DM is validated by measurements. A laser vibrometer is used to measure the displacement of the mirror facesheet, while the actuators are driven by zero-mean, bandlimited, white noise voltage sequence. Using the MOESP system identification algorithm, high-order black-box models are identified with VAF values around 95%. The first resonance frequency identified is 725Hz, and lower than the 974Hz expected from the analytical model. This is attributed to the variations in actuator properties, such as actuator stiffness. The power dissipation in each actuator of the 050mm mirror to correct a typical Von Karmann turbulence spectrum is ~ 1.5m W

    CMOS optical centroid processor for an integrated Shack-Hartmann wavefront sensor

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    A Shack Hartmann wavefront sensor is used to detect the distortion of light in an optical wavefront. It does this by sampling the wavefront with an array of lenslets and measuring the displacement of focused spots from reference positions. These displacements are linearly related to the local wavefront tilts from which the entire wavefront can be reconstructed. In most Shack Hartmann wavefront sensors, a CCD is used to sample the entire wavefront, typically at a rate of 25 to 60 Hz, and a whole frame of light spots is read out before their positions are processed. This results in a data bottleneck. In this design, parallel processing is achieved by incorporating local centroid processing for each focused spot, thereby requiring only reduced bandwidth data to be transferred off-chip at a high rate. To incorporate centroid processing at the sensor level requires high levels of circuit integration not possible with a CCD technology. Instead a standard 0.7J..lmCMOS technology was used but photodetector structures for this technology are not well characterised. As such characterisation of several common photodiode structures was carried out which showed good responsitivity of the order of 0.3 AIW. Prior to fabrication on-chip, a hardware emulation system using a reprogrammable FPGA was built which implemented the centroiding algorithm successfully. Subsequently, the design was implemented as a single-chip CMOS solution. The fabricated optical centroid processor successfully computed and transmitted the centroids at a rate of more than 2.4 kHz, which when integrated as an array of tilt sensors will allow a data rate that is independent of the number of tilt sensors' employed. Besides removing the data bottleneck present in current systems, the design also offers advantages in terms of power consumption, system size and cost. The design was also shown to be extremely scalable to a complete low cost real time adaptive optics system
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