Functional Verification of Large-integers Circuits using a Cosimulation-based Approach

Cryptography and computational algebra designs are complex systems based on modular arithmetic and build on multi-level modules where bit-width is generally larger than 64-bit. Because of their particularity, such designs pose a real challenge for verification, in part because large-integer’s functions are not supported in actual hardware description languages (HDLs), therefore limiting the HDL testbench utility. In another hand, high-level verification approach proved its efficiency in the last decade over HDL testbench technique by raising the latter at a higher abstraction level. In this work, we propose a high-level platform to verify such designs, by leveraging the capabilities of a popular tool (Matlab/Simulink) to meet the requirements of a cycle accurate verification without bit-size restrictions and in multi-level inside the design architecture. The proposed high-level platform is augmented by an assertion-based verification to complete the verification coverage. The platform experimental results of the testcase provided good evidence of its performance and re-usability

Methoden und Beschreibungssprachen zur Modellierung und Verifikation vonSchaltungen und Systemen: MBMV 2015 - Tagungsband, Chemnitz, 03. - 04. März 2015

Der Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2015) findet nun schon zum 18. mal statt. Ausrichter sind in diesem Jahr die Professur Schaltkreis- und Systementwurf der Technischen Universität Chemnitz und das Steinbeis-Forschungszentrum Systementwurf und Test. Der Workshop hat es sich zum Ziel gesetzt, neueste Trends, Ergebnisse und aktuelle Probleme auf dem Gebiet der Methoden zur Modellierung und Verifikation sowie der Beschreibungssprachen digitaler, analoger und Mixed-Signal-Schaltungen zu diskutieren. Er soll somit ein Forum zum Ideenaustausch sein. Weiterhin bietet der Workshop eine Plattform für den Austausch zwischen Forschung und Industrie sowie zur Pflege bestehender und zur Knüpfung neuer Kontakte. Jungen Wissenschaftlern erlaubt er, ihre Ideen und Ansätze einem breiten Publikum aus Wissenschaft und Wirtschaft zu präsentieren und im Rahmen der Veranstaltung auch fundiert zu diskutieren. Sein langjähriges Bestehen hat ihn zu einer festen Größe in vielen Veranstaltungskalendern gemacht. Traditionell sind auch die Treffen der ITGFachgruppen an den Workshop angegliedert. In diesem Jahr nutzen zwei im Rahmen der InnoProfile-Transfer-Initiative durch das Bundesministerium für Bildung und Forschung geförderte Projekte den Workshop, um in zwei eigenen Tracks ihre Forschungsergebnisse einem breiten Publikum zu präsentieren. Vertreter der Projekte Generische Plattform für Systemzuverlässigkeit und Verifikation (GPZV) und GINKO - Generische Infrastruktur zur nahtlosen energetischen Kopplung von Elektrofahrzeugen stellen Teile ihrer gegenwärtigen Arbeiten vor. Dies bereichert denWorkshop durch zusätzliche Themenschwerpunkte und bietet eine wertvolle Ergänzung zu den Beiträgen der Autoren. [... aus dem Vorwort

On mixed abstraction, languages and simulation approach to refinement with SystemC AMS

Executable specifications and simulations arecornerstone to system design flows. Complex mixed signalembedded systems can be specified with SystemC AMSwhich supports abstraction and extensible models of computation. The language contains semantics for moduleconnections and synchronization required in analog anddigital interaction. Through the synchronization layer, user defined models of computation, solvers and simulators can be unified in the SystemC AMS simulator for achieving low level abstraction and model refinement. These improvements assist in amplifying model aspects and their contribution to the overall system behavior. This work presents cosimulating refined models with timed data flow paradigm of SystemC AMS. The methodology uses Cbased interaction between simulators. An RTL model ofdata encryption standard is demonstrated as an example.The methodology is flexible and can be applied in earlydesign decision trade off, architecture experimentation and particularly for model refinement and critical behavior analysis

Development of a 5V Digital Cell Library for use with the Peregrine Semiconductor Silicon-on-Sapphire Process

The scope of the thesis work presented here is to develop a standard digital cell library operable at 5V of power supply and up to the temperatures of 125C using Peregrine 0.5m2 3.3V CMOS process. Peregrine 0.5m process was selected as a result of its availability via commercial foundry at moderate cost radiation and high temperature tolerant properties. Testing data was obtained showing no measurable gate tunneling at gate voltages below 8.5V and no source to drain avalanche below 5.5V ensuring safe operation below the 5V design corners of 5.5V. Device geometries are selected to meet drive current requirement of 1mA and acceptable Ion/Ioff ratios at high temperature. Layouts for cells, schematic, symbolic and abstract views were generated. Timing, power and area characterization data is realized in several formats compatible with Cadence and Synopsys synthesizer, place & route and simulation tools. A test chip for delay chains with single input and multi-input combinatorial gates were designed and fabricated as a part of the validation on silicon. Measured data at room temperature is well in agreement with SignalStorm's data. At 125C, delay chains performed faster in silicon by up to 25% as compared with simulated data obtained using typical model. Device characteristics for rn and rp device are obtained and percentage variations in their Id-Vd characteristics with models are calculated. Variation in test data for the test chip as compared to the simulated data is observed to be consistent with the device current variation plotted across process corners. Adherence of the targeted design specifications (from simulation) with the actual measured values verifies the cell library's functionality, timing and power parameters.School of Electrical & Computer Engineerin

Doctor of Philosophy

dissertationThe design of integrated circuit (IC) requires an exhaustive verification and a thorough test mechanism to ensure the functionality and robustness of the circuit. This dissertation employs the theory of relative timing that has the advantage of enabling designers to create designs that have significant power and performance over traditional clocked designs. Research has been carried out to enable the relative timing approach to be supported by commercial electronic design automation (EDA) tools. This allows asynchronous and sequential designs to be designed using commercial cad tools. However, two very significant holes in the flow exist: the lack of support for timing verification and manufacturing test. Relative timing (RT) utilizes circuit delay to enforce and measure event sequencing on circuit design. Asynchronous circuits can optimize power-performance product by adjusting the circuit timing. A thorough analysis on the timing characteristic of each and every timing path is required to ensure the robustness and correctness of RT designs. All timing paths have to conform to the circuit timing constraints. This dissertation addresses back-end design robustness by validating full cyclical path timing verification with static timing analysis and implementing design for testability (DFT). Circuit reliability and correctness are necessary aspects for the technology to become commercially ready. In this study, scan-chain, a commercial DFT implementation, is applied to burst-mode RT designs. In addition, a novel testing approach is developed along with scan-chain to over achieve 90% fault coverage on two fault models: stuck-at fault model and delay fault model. This work evaluates the cost of DFT and its coverage trade-off then determines the best implementation. Designs such as a 64-point fast Fourier transform (FFT) design, an I2C design, and a mixed-signal design are built to demonstrate power, area, performance advantages of the relative timing methodology and are used as a platform for developing the backend robustness. Results are verified by performing post-silicon timing validation and test. This work strengthens overall relative timed circuit flow, reliability, and testability

Design and implementation of a bootrom in a Linux capable RISC-V processor

El moviment de codi obert promet revolucionar el món del maquinari igual que el programari ha revolucionat. Gràcies a l'arquitectura de conjunt d'instruccions o ISA (de l'anglès Instruction Set Architecture) RISC-V de codi obert, molts projectes s'estan obrint camí per oferir una alternativa a l'hermètic i privatiu món de l'arquitectura de computadors. En aquest context neix el projecte DRAC, les sigles del qual fan referència, de l'anglès, a Designing RISC-V-based Accelerators for next-generation Computers. Aquest projecte, liderat pel Barcelona Supercomputing Center (BSC), desenvolupa processadors i acceleradors basats en la tecnologia RISC-V, amb l'objectiu d'accelerar tasques de seguretat, medicina personalitzada i navegació autònoma. Aquesta tesi té com a propòsit dissenyar, implementar i verificar una bootrom pel SoC (de l'anglès System on Chip) de 64 bits DRAC 22 nm. Aquest SoC integra un processador RISC-V de 7 etapes anomenat Sargantana. El disseny del SoC, basat en l'anterior \textit{tape-out} anomenat PreDRAC, es divideix en dues parts. Una part conté tots els components orientats a l'ASIC; l'altra conté els elements orientats a la FPGA. Una de les raons principals d'aquesta divisió és que no existia una bootrom orientada a ASIC i, per tant, calia utilitzar la FPGA per arrencar el xip. Amb la integració de la bootrom desenvolupada en aquesta tesi, el SoC serà capaç d'arrencar per ell mateix, eliminant la part orientada a la FPGA del disseny del SoC.The open-source movement promises to revolutionize the hardware world just as it has revolutionized software. Thanks to the open-source RISC-V instruction set architecture (ISA), many projects are making their way to offer an alternative in the hermetic and proprietary world of computer architecture. The DRAC project, whose acronym refers to Designing RISC-V-based Accelerators for next-generation Computers, was created in this context. This project, led by the Barcelona Supercomputing Center (BSC), develops processors and accelerators based on RISC-V technology, and their purpose is to accelerate security tasks, personalized medicine and autonomous navigation. This thesis aims to design, implement and verify a bootrom for the 64-bit DRAC 22 nm System on Chip (SoC). This SoC integrates an in-order 7-stage RISC-V core called Sargantana. The SoC design, based on the previous tape-out PreDRAC, is divided into two parts. One part contains all the ASIC-oriented components; the other contains the FPGA-oriented components. One of the main reasons for this division is that there was no ASIC-oriented bootrom, and therefore, it was necessary to use the FPGA to boot the chip. With the integration of the bootrom developed in this thesis, the SoC will be able to boot by itself, eliminating the FPGA-oriented part of the SoC design